arXiv subjects

B. Shojaei

Publications and source records attributed to B. Shojaei.

4 recordsLinked to original sources

arXiv2022

Planar Josephson Junctions Templated by Nanowire Shadowing

More and more materials, with a growing variety of properties, are built into electronic devices. This is motivated both by increased device performance and by the studies of materials themselves. An important type of device is a Josephson junction based on the proximity effect between a quantum material and a superconductor, useful for fundamental research as well as for quantum and other technologies. When both junction contacts are placed on the same surface, such as a two-dimensional material, the junction is called ``planar". One outstanding challenge is that not all materials are amenable to the standard planar junction fabrication. The device quality, rather than the intrinsic characteristics, may be defining the results. Here, we introduce a technique in which nanowires are placed on the surface and act as a shadow mask for the superconductor. The advantages are that the smallest dimension is determined by the nanowire diameter and does not require lithography, and that the junction is not exposed to chemicals such as etchants. We demonstrate this method with an InAs quantum well, using two superconductors - Al and Sn, and two semiconductor nanowires - InAs and InSb. The junctions exhibit critical current levels consistent with transparent interfaces and uniform width. We show that the template nanowire can be operated as a self-aligned electrostatic gate. Beyond single junctions, we create SQUIDs with two gate-tunable junctions. We suggest that our method can be used for a large variety of quantum materials including van der Waals layers, topological insulators, Weyl semimetals and future materials for which proximity effect devices is a promising research avenue.

cond-mat.mes-hall↗

arXiv2016

Proximity Effect Transfer from NbTi into a Semiconductor Heterostructure via Epitaxial Aluminum

We demonstrate the transfer of the superconducting properties of NbTi---a large-gap high-critical-field superconductor---into an InAs heterostructure via a thin intermediate layer of epitaxial Al. Two device geometries, a Josephson junction and a gate-defined quantum point contact, are used to characterize interface transparency and the two-step proximity effect. In the Josephson junction, multiple Andreev reflection reveal near-unity transparency, with an induced gap $Δ^*=0.50~\mathrm{meV}$ and a critical temperature of $7.8~\mathrm{K}$. Tunneling spectroscopy yields a hard induced gap in the InAs adjacent to the superconductor of $Δ^*=0.43~\mathrm{meV}$ with substructure characteristic of both Al and NbTi.

cond-mat.mes-hall↗

arXiv2016

On the limits to mobility in InAs quantum wells with nearly lattice-matched barriers

The growth and the density dependence of the low temperature mobility of a series of two-dimensional electron systems confined to un-intentionally doped, low extended defect density InAs quantum wells with Al$_{1-x}$Ga$_{x}$Sb barriers are reported. The electron mobility limiting scattering mechanisms were determined by utilizing dual-gated devices to study the dependence of mobility on carrier density and electric field independently. Analysis of the possible scattering mechanisms indicate the mobility was limited primarily by rough interfaces in narrow quantum wells and a combination of alloy disorder and interface roughness in wide wells at high carrier density within the first occupied electronic sub-band. At low carrier density the functional dependence of the mobility on carrier density provided evidence of coulombic scattering from charged defects. A gate-tuned electron mobility exceeding 750,000 cm$^{2}$/Vs was achieved at a sample temperature of 2 K.

cond-mat.mtrl-sci↗

arXiv2014

Gating of high-mobility InAs metamorphic heterostructures

We investigate the performance of gate-defined devices fabricated on high mobility InAs metamorphic heterostructures. We find that heterostructures capped with In$_{0.75}$Ga$_{0.25}$As often show signs of parallel conduction due to proximity of their surface Fermi level to the conduction band minimum. Here, we introduce a technique that can be used to estimate the density of this surface charge that involves cool-downs from room temperature under gate bias. We have been able to remove the parallel conduction under high positive bias, but achieving full depletion has proven difficult. We find that by using In$_{0.75}$Al$_{0.25}$As as the barrier without an In$_{0.75}$Ga$_{0.25}$As capping, a drastic reduction in parallel conduction can be achieved. Our studies show that this does not change the transport properties of the quantum well significantly. We achieved full depletion in InAlAs capped heterostructures with non-hysteretic gating response suitable for fabrication of gate-defined mesoscopic devices.

cond-mat.mes-hall↗