arXiv subjects

Baris Taskin

Publications and source records attributed to Baris Taskin.

5 recordsLinked to original sources

arXiv2026

ROA-Based Subharmonic Injection Locking for Oscillator-Based Ising Machines

This paper introduces on-chip integrated rotary traveling wave oscillators (RTWOs) organized into rotary oscillator array (ROA) bricks as an external perturbation to induce subharmonic injection locking (SHIL) in oscillator-based Ising machines (OIMs). The implementation of SHILs on chip is challenging, as the frequency of SHILs must be multiples of the operating frequency of the OIM nodes, with on-chip variations affecting the phase, degrading the SHIL process. This impedes the scaling of OIM implementations, regardless of the topology of Ising nodes, coupling or graph mapping mechanisms. The ROA brick topology implementation of RTWOs generates high frequency signals that are shown to provide a stable 2.31 GHz SHIL signal under process, voltage, and temperature (PVT) variations. Under PVT variations, distributed ring oscillator-based SHILs (ROSC-SHIL) fail to perform injection locking while the proposed ROA brick-based SHIL (ROA-SHIL) preserve 93% to 97% accuracy (the same accuracy of an ideal SHIL signal) in the OIM solutions of a sample 324-node max-cut problem. The driving strength and floorplan of the ROA brick are also shown to be amenable for scaling with an energy-to-solution impact of 2.49 nJ for the proposed ROA-SHIL.

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arXiv2026

An ASIC Emulated Oscillator Ising/Potts Machine Solving Combinatorial Optimization Problems

Oscillator-based Ising/Potts machines (OIMs/OPMs) are promising hardware accelerators for NP-hard combinatorial optimization problems using coupled oscillator synchronization dynamics. Analog OIMs/OPMs offer speed advantages but have limited coupling resolution, process variation susceptibility, and scalability issues, while digital GPU/CPU emulations provide flexibility but suffer from irregular memory access patterns and energy inefficiency. This work presents a custom ASIC architecture that digitally emulates OIM/OPM dynamics using simplified fixedpoint Kuramoto model equations. The scalable design features processing elements with direct interconnections, eliminating shared memory bottleneck while maintaining digital programmability and precision. A 20x20 processing element array with king's graph connectivity is prototyped and evaluated via post-layout simulations on unweighted/weighted max-cut and graph coloring problems, achieving 97-100% maximum accuracy with significant speed and energy improvements over general-purpose platforms, demonstrating the viability of algorithmically codesigned ASICs.

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arXiv2025

GPU-Accelerated Simulated Oscillator Ising/Potts Machine Solving Combinatorial Optimization Problems

Oscillator-based Ising machines (OIMs) and oscillator-based Potts machines (OPMs) have emerged as promising hardware accelerators for solving NP-hard combinatorial optimization problems by leveraging the phase dynamics of coupled oscillators. In this work, a GPU-accelerated simulated OIM/OPM digital computation framework capable of solving combinatorial optimization problems is presented. The proposed implementation harnesses the parallel processing capabilities of GPUs to simulate large-scale OIM/OPMs, leveraging the advantages of digital computing to offer high precision, programmability, and scalability. The performance of the proposed GPU framework is evaluated on the max-cut problems from the GSET benchmark dataset and graph coloring problems from the SATLIB benchmarks dataset, demonstrating competitive speed and accuracy in tackling large-scale problems. The results from simulations, reaching up to 11295x speed-up over CPUs with up to 99% accuracy, establish this framework as a scalable, massively parallelized, and high-fidelity digital realization of OIM/OPMs.

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arXiv2025

A Multi-Stage Potts Machine based on Coupled CMOS Ring Oscillators

This work presents a multi-stage coupled ring oscillator based Potts machine, designed with phase-shifted Sub Harmonic-Injection-Locking (SHIL) to represent multi valued Potts spins at different solution stages with os cillator phases. The proposed Potts machine is able to solve a certain class of combinatorial optimization prob lems that natively require multivalued spins with a divide and-conquer approach, facilitated through the alternating phase-shifted SHILs acting on the oscillators. The pro posed architecture eliminates the need for any external in termediary mappings or usage of external memory, as the influence of SHIL allows oscillators to act as both mem ory and computation units. Planar 4-coloring problems of sizes up to 2116 nodes are mapped to the proposed architecture. Simulations demonstrate that the proposed Potts machine provides exact solutions for smaller prob lems (e.g. 49 nodes) and generates solutions reaching up to 97% accuracy for larger problems (e.g. 2116 nodes).

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arXiv2025

Multi-Phase Coupled CMOS Ring Oscillator based Potts Machine

This paper presents a coupled ring oscillator based Potts ma chine to solve NP-hard combinatorial optimization problems (COPs). Potts model is a generalization of the Ising model, cap turing multivalued spins in contrast to the binary-valued spins allowed in the Ising model. Similar to recent literature on Ising machines, the proposed architecture of Potts machines imple ments the Potts model with interacting spins represented by cou pled ring oscillators. Unlike Ising machines which are limited to two spin values, Potts machines model COPs that require a larger number of spin values. A major novelty of the proposed Potts machine is the utilization of the N-SHIL (Sub-Harmonic Injection Locking) mechanism, where multiple stable phases are obtained from a single (i.e. ring) oscillator. In evaluation, 3 coloring problems from the DIMACS SATBLIB benchmark and two randomly generated larger problems are mapped to the pro posed architecture. The proposed architecture is demonstrated to solve problems of varying size with 89% to 92% accuracy averaged over multiple iterations. The simulation results show that there is no degradation in accuracy, no significant increase in solution time, and only a linear increase in power dissipation with increasing problem sizes up to 2000 nodes.

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