arXiv subjects

Behnaz Ranjbar

Publications and source records attributed to Behnaz Ranjbar.

4 recordsLinked to original sources

arXiv2026

Autonomous Systems Dependability in the era of AI: Design Challenges in Safety, Security, Reliability and Certification

The design of embedded safety-critical systems such as those used in next-generation automotive and autonomous platforms, is increasingly challenged by escalating system complexity, hardware-software heterogeneity, and the integration of intelligent, data-driven components. Ensuring dependability in such systems requires a holistic approach that spans multiple abstraction layers and encompasses both design- and run-time assurance. Traditional methods for reliability, safety, and security management often fall short in addressing the dynamic and uncertain behaviors introduced by Artificial Intelligence (AI) and Machine Learning (ML) components, especially under stringent real-time, power, and safety constraints. While AI and ML offer powerful predictive, adaptive, and self-optimizing capabilities that can enhance system dependability, their inherent non-determinism, data-dependence, and lack of formal guarantees introduce new challenges for verification, validation, and certification. This paper explores emerging methodologies, architectures, and frameworks for designing dependable autonomous and embedded systems in the era of AI. It highlight advances in reliability modeling, secure system design, and certification approaches that account for imperfect, learning-enabled components, aiming to bridge the gap between AI innovation and certifiable system-level dependability.

cs.AI↗

arXiv2026

AnTi-MiCS: Analytical Framework for Bounding Time in Embedded Mixed-Criticality Systems

In Mixed-Criticality (MC) systems, although the high Worst-Case Execution Time (WCET) serves as a conservative upper bound representing the task's maximum execution time under all conditions, obtaining a low WCET is essential for representing realistic executions and improving utilization and Quality-of-Service (QoS). Nevertheless, determining appropriate low WCET(s) for lower-criticality (LO) modes poses a significant challenge. Opting for a very low value of this WCET enhances processor utilization by scheduling more tasks in LO mode. Conversely, employing a larger WCET ensures fewer mode switches, thereby enhancing QoS, albeit at the cost of processor utilization. This paper proposes an analytical approach, AnTi-MiCS, to determine the appropriate low WCET through design-time analysis of task executions. In some cases, a single low WCET may not be adequate to capture large variations in the execution time distribution, for example, in scenarios like bimodal distributions. Therefore, we further propose a scalable approach, MulTi-MiCS, to compute multiple appropriate low WCETs. This approach exploits the temporal correlation between subsequent inputs presented to the application. Experimental results, conducted on a real platform with embedded real-time benchmarks, demonstrate the efficacy of our proposed scheme, in which QoS is improved by 30.27% on average while reducing utilization waste by 35.89%, compared to existing approaches. Besides, MulTi-MiCS improves QoS by 6.41% compared to AnTi-MiCS while reducing utilization waste by 8.23%.

cs.DC↗

arXiv2021

Toward the Design of Fault-Tolerance- and Peak- Power-Aware Multi-Core Mixed-Criticality Systems

Mixed-Criticality (MC) systems have recently been devised to address the requirements of real-time systems in industrial applications, where the system runs tasks with different criticality levels on a single platform. In some workloads, a high-critically task might overrun and overload the system, or a fault can occur during the execution. However, these systems must be fault-tolerant and guarantee the correct execution of all high-criticality tasks by their deadlines to avoid catastrophic consequences, in any situation. Furthermore, in these MC systems, the peak power consumption of the system may increase, especially in an overload situation and exceed the processor Thermal Design Power (TDP) constraint. This may cause generating heat beyond the cooling capacity, resulting the system stop to avoid excessive heat and halting the processor. In this paper, we propose a technique for dependent dual-criticality tasks in fault-tolerant multi-core MC systems to manage peak power consumption and temperature. The technique develops a tree of possible task mapping and scheduling at design-time to cover all possible scenarios and reduce the low-criticality task drop rate in the high-criticality mode. At run-time, the system exploits the tree to select a proper schedule according to fault occurrences and criticality mode changes. Experimental results show that the average task schedulability is 74.14% on average for the proposed method, while the peak power consumption and maximum temperature are improved by 16.65% and 14.9 C on average, respectively, compared to a recent work. In addition, for a real-life application, our method reduces the peak power and maximum temperature by up to 20.06% and 5 C, respectively, compared to a state-of-the-art approach.

cs.DC↗

arXiv2020

Power-Aware Run-Time Scheduler for Mixed-Criticality Systems on Multi-Core Platform

In modern multi-core Mixed-Criticality (MC) systems, a rise in peak power consumption due to parallel execution of tasks with maximum frequency, specially in the overload situation, may lead to thermal issues, which may affect the reliability and timeliness of MC systems. Therefore, managing peak power consumption has become imperative in multi-core MC systems. In this regard, we propose an online peak power and thermal management heuristic for multi-core MC systems. This heuristic reduces the peak power consumption of the system as much as possible during runtime by exploiting dynamic slack and per-cluster Dynamic Voltage and Frequency Scaling (DVFS). Specifically, our approach examines multiple tasks ahead to determine the most appropriate one for slack assignment, that has the most impact on the system peak power and temperature. However, changing the frequency and selecting a proper task for slack assignment and a proper core for task re-mapping at runtime can be time-consuming and may cause deadline violation which is not admissible for high-criticality tasks. Therefore, we analyze and then optimize our run-time scheduler and evaluate it for various platforms. The proposed approach is experimentally validated on the ODROID-XU3 (DVFS-enabled heterogeneous multi-core platform) with various embedded real-time benchmarks. Results show that our heuristic achieves up to 5.25% reduction in system peak power and 20.33\% reduction in maximum temperature compared to an existing method while meeting deadline constraints in different criticality modes.

cs.DC↗