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Bengu Bilgic Keskin

Publications and source records attributed to Bengu Bilgic Keskin.

2 recordsLinked to original sources

Spectral Efficiency Analysis of Massive MIMO-OFDM Systems with Double Quantization

Massive multiple-input multiple-output (MIMO) achieves a high spectral efficiency (SE) by employing a large number of receive antennas in the uplink. Employing many receive antennas requires a large number of analog-to-digital converters (ADCs) and a high fronthaul data rate. Low-resolution ADCs can reduce power consumption and cost, while fronthaul quantization can reduce the required fronthaul data rate, at the expense of quantization distortion at both stages. In wideband orthogonal frequency-division multiplexing systems, ADC quantization is performed in the time domain, while fronthaul quantization may be applied after the discrete Fourier transform to transmit only active subcarriers. In this study, we investigate the achievable uplink SE over fronthaul links under double quantization and imperfect channel estimation. We derive a linear minimum mean-squared error channel estimator from the double-quantized pilot observations and obtain an achievable SE using the use-and-then-forget bound. Numerical results demonstrate that the ADC and fronthaul quantization resolutions have comparable impacts on the achievable SE. When the two resolutions differ, the lower resolution becomes the dominant factor limiting the SE. Furthermore, our numerical results show that six-bit ADC and fronthaul quantization achieve more than 90% of the SE attained in the ideal case.

cs.IT↗

RFNoC-Based FPGA Offloading for Fully Programmable PHY Acceleration

Hardware acceleration has emerged as a key research topic for supporting computationally intensive signal processing and artificial intelligence applications in 6G research and development studies. This paper presents an RF Network on Chip (RFNoC) based hardware acceleration framework that offloads key physical layer procedures to a field programmable gate array (FPGA). The proposed design accelerates procedures, including low density parity check codes (LDPC) encoding and decoding, rate matching and unmatching, interleaving and deinterleaving, scrambling and descrambling, and log likelihood ratio estimation. The accelerator is integrated directly into the OpenAirInterface radio access network software, enabling simultaneous use of the FPGA as driver of the radio front end and a high throughput accelerator. The proposed system is validated through real time experiments with a commercial smartphone successfully connecting to the network. The implementation results demonstrate that a throughput of about 900 Mbps is achiievable using a moderate FPGA resource utlization.

eess.SP↗