arXiv subjects

Bin-Han Lu

Publications and source records attributed to Bin-Han Lu.

4 recordsLinked to original sources

arXiv2025

Spectator Leakage Suppression via Invariant Subspace Engineering for CZ Gates in Superconducting Quantum Circuits

Spectator leakage poses a fundamental challenge to scalable quantum computing, particularly as frequency collisions become unavoidable in multi-qubit processors. We introduce a leakage mitigation strategy based on dynamically reshaping the system Hamiltonian. Our technique utilizes a tunable coupler to enforce a block-diagonal structure on the effective Hamiltonian governing near-resonant spectator interactions, confining the gate dynamics to a two-dimensional invariant subspace and thus preventing leakage by construction. On a multi-qubit superconducting processor, we experimentally demonstrate that this dynamic control scheme suppresses leakage rates to the order of $10^{-4}$, across a wide near-resonant detuning range and with up to three simultaneous spectator qubits. These results demonstrate a robust and scalable method that resolves the critical trade-off between dense frequency packing and high-fidelity gate operation. Our work establishes dynamic Hamiltonian engineering as an essential technology for building fault-tolerant quantum computers.

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arXiv2024

Neural Network-Based Frequency Optimization for Superconducting Quantum Chips

Optimizing the frequency configuration of qubits and quantum gates in superconducting quantum chips presents a complex NP-complete optimization challenge. This process is critical for enabling practical control while minimizing decoherence and suppressing significant crosstalk. In this paper, we propose a neural network-based frequency configuration approach. A trained neural network model estimates frequency configuration errors, and an intermediate optimization strategy identifies optimal configurations within localized regions of the chip. The effectiveness of our method is validated through randomized benchmarking and cross-entropy benchmarking. Furthermore, we design a crosstalk-aware hardware-efficient ansatz for variational quantum eigensolvers, achieving improved energy computations.

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arXiv2024

Demonstrating a universal logical gate set in error-detecting surface codes on a superconducting quantum processor

Fault-tolerant quantum computing (FTQC) is essential for achieving large-scale practical quantum computation. Implementing arbitrary FTQC requires the execution of a universal gate set on logical qubits, which is highly challenging. Particularly, in the superconducting system, two-qubit gates on surface code logical qubits have not been realized. Here, we experimentally implement a logical CNOT gate along with arbitrary single-qubit rotation gates on distance-2 surface codes using the superconducting quantum processor \textit{Wukong}, thereby demonstrating a universal logical gate set. In the experiment, we demonstrate the transversal CNOT gate on a two-dimensional topological processor based on a tailored encoding circuit, at the cost of removing the ancilla qubits required for stabilizer measurements. Furthermore, we fault-tolerantly prepare logical Bell states and observe a violation of CHSH inequality, confirming the entanglement between logical qubits. Using the logical CNOT gate and an ancilla logical state, arbitrary single-qubit rotation gates are realized through gate teleportation. All logical gates are characterized on a complete state set and their fidelities are evaluated by logical Pauli transfer matrices. The demonstration of a universal logical gate set and the entangled logical states highlights significant aspects of FTQC on superconducting quantum processors.

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arXiv2021

Special-Purpose Quantum Processor Design

Full connectivity of qubits is necessary for most quantum algorithms, which is difficult to directly implement on Noisy Intermediate-Scale Quantum processors. However, inserting swap gate to enable the two-qubit gates between uncoupled qubits significantly decreases the computation result fidelity. To this end, we propose a Special-Purpose Quantum Processor Design method that can design suitable structures for different quantum algorithms. Our method extends the processor structure from two-dimensional lattice graph to general planar graph and arranges the physical couplers according to the two-qubit gate distribution between the logical qubits of the quantum algorithm and the physical constraints. Experimental results show that our design methodology, compared with other methods, could reduce the number of extra swap gates per two-qubit gate by at least 104.2% on average. Also, our method's advantage over other methods becomes more obvious as the depth and qubit number increase. The result reveals that our method is competitive in improving computation result fidelity and it has the potential to demonstrate quantum advantage under the technical conditions.

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