arXiv subjects

Brian Martinick

Publications and source records attributed to Brian Martinick.

4 recordsLinked to original sources

arXiv2026

Effects of Integrated Heatsinking on Superconductivity in Tantalum Nitride Nanowires at the 300 Millimeter Scale

We report the superconducting properties of tantalum nitride (TaN) nanowires and TaN/copper (TaN/Cu) bilayer nanowires fabricated on 300 mm silicon wafers using CMOS-compatible processes. We evaluate how an integrated Cu heatsink modifies the superconducting response of TaN nanowires by improving thermal dissipation without significantly compromising key superconducting parameters. Through analysis of hysteresis in current-voltage curves, we demonstrate that Cu integration improves heat dissipation, supporting expectations of faster reset times in superconducting nanowire single-photon detectors (SNSPDs), consistent with enhanced heat transfer away from the hot spot. Using the Skocpol-Beasley-Tinkham (SBT) hotspot model, we quantify the Cu-enabled improvement in heat transfer as an approximately 100x increase in the SBT slope parameter beta and effective interfacial heat-transfer efficiency compared to TaN nanowires. The near-unity ratio of critical to retrapping current in TaN/Cu bilayer nanowires provides another evidence of efficient heat removal enabled by the integrated Cu layer. Our results show a zero-temperature Ginzburg-Landau coherence length of 7 nm and a critical temperature of 4.1 K for 39 nm thick TaN nanowires. The nanowires show <5% variation in critical dimensions, room-temperature resistance, residual resistance ratio, critical temperature, and critical current across the 300 mm wafer for all measured linewidths, demonstrating excellent process uniformity and scalability. These results indicate the trade-offs between superconducting performance and heat-sinking efficiency in TaN/Cu bilayer nanowires. They also underscore the viability of wafer-scale fabrication for fast, large-area SNSPD arrays for applications in photonic quantum computing, cosmology, and neuromorphic computing devices.

cond-mat.supr-con↗

arXiv2025

Ta-based Josephson junctions using insulating ALD TaN tunnel barriers

Josephson junctions form the core circuit element in superconducting quantum computing circuits, single flux quantum digital logic circuits, and sensing devices such as SQUIDs. Aluminum oxide has typically been used as the tunnel barrier. Its formation by exposure to low oxygen pressures at room temperature for short periods of time makes it susceptible to aging and limits the thermal budget of downstream processes. In this paper, we report the first demonstration of {\alpha}-Ta/insulating TaN/a-Ta superconductor/insulator/superconductor Josephson junctions fabricated on 300 mm wafers using CMOS-compatible processes. The junctions were fabricated on high-resistivity silicon substrates using standard processes available at 300 mm scale, including 193 nm optical lithography, ALD of TaN in a cluster tool, and chemical mechanical planarization to enable highly planar interfaces. Junction areas ranging from 0.03 um2 to 9 um2 with ALD TaN thickness between 2 nm and 7 nm were characterized. A critical current density of 76 uA/um2 was observed in junctions using 4 nm ALD TaN in the tunnel barrier. The dependence of Jc on ALD TaN layer thickness is analyzed, and the influence of junction geometry, packaging, and temperature on I-V characteristics is discussed. Junctions were retested after a period of 4 months to quantify junction aging. The potential of this novel material system and a 300 mm superconducting junction process flow to fabricate thermally and environmentally stable junctions is discussed. The vision of a Superconducting Quantum Process Design Kit for a Multi-Project Wafer program to enable rapid development and proliferation of superconducting quantum and digital digital logic systems is presented. This work represents the first step towards establishing such a Quantum Foundry, providing access to high quality qubits and single-flux quantum logic circuits at 300 mm wafer scale.

cond-mat.supr-con↗

arXiv2023

Engineering of Niobium Surfaces Through Accelerated Neutral Atom Beam Technology For Quantum Applications

A major roadblock to scalable quantum computing is phase decoherence and energy relaxation caused by qubits interacting with defect-related two-level systems (TLS). Native oxides present on the surfaces of superconducting metals used in quantum devices are acknowledged to be a source of TLS that decrease qubit coherence times. Reducing microwave loss by surface engineering (i.e., replacing uncontrolled native oxide of superconducting metals with a thin, stable surface with predictable characteristics) can be a key enabler for pushing performance forward with devices of higher quality factor. In this work, we present a novel approach to replace the native oxide of niobium (typically formed in an uncontrolled fashion when its pristine surface is exposed to air) with an engineered oxide, using a room-temperature process that leverages Accelerated Neutral Atom Beam (ANAB) technology at 300 mm wafer scale. This ANAB beam is composed of a mixture of argon and oxygen, with tunable energy per atom, which is rastered across the wafer surface. The ANAB-engineered Nb-oxide thickness was found to vary from 2 nm to 6 nm depending on ANAB process parameters. Modeling of variable-energy XPS data confirm thickness and compositional control of the Nb surface oxide by the ANAB process. These results correlate well with those from transmission electron microscopy and X-ray reflectometry. Since ANAB is broadly applicable to material surfaces, the present study indicates its promise for modification of the surfaces of superconducting quantum circuits to achieve longer coherence times.

physics.app-ph↗

arXiv2023

Chemical Mechanical Planarization for Ta-based Superconducting Quantum Devices

We report on the development of a chemical mechanical planarization (CMP) process for thick damascene Ta structures with pattern feature sizes down to 100 nm. This CMP process is the core of the fabrication sequence for scalable superconducting integrated circuits at 300 mm wafer scale. This work has established the elements of the various CMP-related design rules that can be followed by a designer for the layout of circuits that include Ta-based coplanar waveguide resonators, capacitors, and interconnects for tantalum-based qubits and single flux quantum (SFQ) circuits. The fabrication of these structures utilizes 193 nm optical lithography, along with 300 mm process tools for dielectric deposition, reactive ion etch, wet-clean, CMP and in-line metrology, all tools typical for a 300 mm wafer CMOS foundry. Process development was guided by measurements of physical and electrical characteristics of the planarized structures. Physical characterization such as atomic force microscopy across the 300 mm wafer surface showed local topography was less than 5 nm. Electrical characterization confirmed low leakage at room temperature, and less than 12% within wafer sheet resistance variation, for damascene Ta line-widths ranging from 100 nm to 3 {\mu}m. Run-to-run reproducibility was also evaluated. Effects of process integration choices including deposited thickness of Ta are discussed.

physics.app-ph↗