arXiv subjects

Carlo Condo

Publications and source records attributed to Carlo Condo.

At least 19 recordsLinked to original sources

arXiv2024

A 95.5Gb/s 29.6ns worst-case latency ORBGRAND decoder for 6G xURLLC

Ultra-Reliable Low-Latency Communications (URLLC) in both 5G and 6G demand high throughput and short latency with low error rates. Guessing Random Additive Noise Decoding (GRAND) and Ordered Reliability Bits GRAND (ORBGRAND) are powerful universal decoding algorithms that work well with short, high-rate codes. As short forward error correcting codes can help limiting latency, and code unification in 6G calls for flexible, possibly code-agnostic decoders, GRAND and ORBGRAND are well suited to tackle 6G URLLC. This work proposes a ultra-high, constant speed ORBGRAND decoder architecture with very low worst-case and average latency. Compared to a baseline architecture, through out-of-order output, aggressive clock gating, and selective programmability, the decoder reduces area, power, and average latency by 15.5%, 19.4%, and 56%, respectively. In 3nm FinFET technology, it achieves a constant throughput of 95.49Gb/s, with 29.59ns worst-case latency and 13.02ns on average.

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arXiv2022

Iterative Soft-Input Soft-Output Decoding with Ordered Reliability Bits GRAND

Guessing Random Additive Noise Decoding (GRAND) is a universal decoding algorithm that can be used to perform maximum likelihood decoding. It attempts to find the errors introduced by the channel by generating a sequence of possible error vectors in order of likelihood of occurrence and applying them to the received vector. Ordered reliability bits GRAND (ORBGRAND) integrates soft information received from the channel to refine the error vector sequence. In this work, ORBGRAND is modified to produce a soft output, to enable its use as an iterative soft-input soft-output (SISO) decoder. Three techniques specific to iterative GRAND-based decoding are then proposed to improve the error-correction performance and decrease computational complexity and latency. Using the OFEC code as a case study, the proposed techniques are evaluated, yielding substantial performance gain and astounding complexity reduction of 48\% to 85\% with respect to the baseline SISO ORBGRAND.

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arXiv2022

A fixed latency ORBGRAND decoder architecture with LUT-aided error-pattern scheduling

Guessing Random Additive Noise Decoding (GRAND) is a universal decoding algorithm that has been recently proposed as a practical way to perform maximum likelihood decoding. It generates a sequence of possible error patterns and applies them to the received vector, checking if the result is a valid codeword. Ordered reliability bits GRAND (ORBGRAND) improves on GRAND by considering soft information received from the channel. Both GRAND and ORBGRAND have been implemented in hardware, focusing on average performance, sacrificing worst case throughput and latency. In this work, an improved pattern schedule for ORBGRAND is proposed. It provides $>0.5$ dB gain over the standard schedule at a block error rate $\le 10^{-5}$, and outperforms more complex GRAND flavors with a fraction of the complexity. The proposed schedule is used within a novel code-agnositic decoder architecture: the decoder guarantees fixed high throughput and low latency, making it attractive for latency-constrained applications. It outperforms the worst-case performance of decoders by orders of magnitude, and outperforms many best-case figures. Decoding a code of length 128, it achieves a throughput of $79.21$ Gb/s with $58.49$ ns latency, yielding better energy efficiency and comparable area efficiency with respect to the state of the art.

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arXiv2021

High-performance low-complexity error pattern generation for ORBGRAND decoding

Guessing Random Additive Noise Decoding (GRAND) is a recently proposed decoding method searching for the error pattern applied to the transmitted codeword. Ordered reliability bit GRAND (ORBGRAND) uses soft channel information to reorder entries of error patterns, generating them according to a fixed schedule, i.e. their logistic weight. In this paper, we show that every good ORBGRAND scheduling should follow an universal partial order, and we present an algorithm to generate the logistic weight order accordingly. We then propose an improved error pattern schedule that can improve the performance of ORBGRAND of 0.5dB at a block error rate (BLER) of $10^{-5}$, with increasing gains as the BLER decreases. This schedule can be closely approximated with a low-complexity generation algorithm that is shown to incur no BLER degradation.

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arXiv2021

Input-distribution-aware parallel decoding of block codes

Many channel decoders rely on parallel decoding attempts to achieve good performance with acceptable latency. However, most of the time fewer attempts than the foreseen maximum are sufficient for successful decoding. Input-distribution-aware (IDA) decoding allows to determine the parallelism of polar code list decoders by observing the distribution of channel information. In this work, IDA decoding is proven to be effective with different codes and decoding algorithms as well. Two techniques, M-IDA and MD-IDA, are proposed: they exploit the sampling of the input distribution inherent to particular decoding algorithms to perform low-cost IDA decoding. Simulation results on the decoding of BCH codes via the Chase and ORBGRAND algorithms show that they perform at least as well as the original IDA decoding, allowing to reduce run-time complexity down to 17% and 67\% with minimal error correction degradation.

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arXiv2021

Staircase codes with non-systematic polar codes

In this work we propose an encoding and decoding framework for staircase codes based on non-systematic polar codes as component codes. The staircase structure allows for efficient parallelized decoding, while the polar component codes allow to benefit from the flexible structure and efficient soft-decision decoding algorithms. To enhance the performance of the polar staircase codes, we concatenate the polar component codes with cyclic redundancy check (CRC) outer codes, and we add interleavers within the staircase structure that are specific to polar code properties. The CRCs also allow to substantially reduce the decoding complexity. Simulation results evaluate the gain brought by our proposed techniques, and analyze the dependence of the error-correction performance on code and decoder parameters. Comparison with the state of the art on staircase polar codes shows an improvement in BER up to 0.9~dB, or considerable complexity reduction at the same BER.

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arXiv2021

Sliding Window Polar Codes

We propose a novel coupling technique for the design of polar codes of length N, making them decodable through a sliding window of size M < N. This feature allows to reduce the computational complexity of the decoder, an important possibility in wireless communication downlink scenarios. Our approach is based on the design of an ad-hoc kernel to be inserted in a multi-kernel polar code framework; this structure enables the sliding window decoding of the code. Simulation results show that the proposed sliding window polar codes outperform the independent blocks transmission in the proposed scenario, at the cost of a negligible decoding overhead.

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arXiv2021

Input-distribution-aware successive cancellation list decoding of polar codes

Polar codes are linear block codes that can achieve channel capacity at infinite code length. Successive cancellation list (SCL) decoding relies on a set of parallel decoders; it yields good error-correction performance at finite code length, at the cost of increased implementation complexity and power consumption. Current efforts in literature focus on design-time decoder complexity reduction, while lacking practical run-time power reduction methods. In this work, input-distribution-aware SCL (IDA-SCL) decoding is proposed, that allows to determine the parallelism to adopt by performing simple observations on the input of the decoder. This technique guarantees fixed, short latency and allows hardware SCL decoders to dynamically shut down part of the internal parallelism before each decoding process. It can be combined with existing complexity- and power- reduction techniques. Simulation results show that IDA-SCL can reduce the run-time complexity of SCL of up to 50\%.

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arXiv2020

Generalized Fast Decoding of Polar Codes

Research on polar codes has been constantly gaining attention over the last decade, by academia and industry alike, thanks to their capacity-achieving error-correction performance and low-complexity decoding algorithms. Recently, they have been selected as one of the coding schemes in the $5^{th}$ generation wireless standard (5G). Over the years various polar code decoding algorithms, like SC-list (SCL), have been proposed to improve the mediocre performance of the successive cancellation (SC) decoding algorithm for finite code lengths; however, like SC, they suffer from long decoding latency. Fast decoding of polar codes tries to overcome this problem by identifying particular subcodes in the polar code and decoding them with efficient decoders. In this work, we introduce a generalized approach to fast decoding of polar codes to further reduce SC-based decoding latency. We propose three multi-node polar code subcodes whose identification patterns include most of the existing subcodes, extending them to SCL decoding, and allow to apply fast decoding to larger subsets of bits. Without any error-correction performance degradation, the proposed technique shows up to $23.6\%$ and $29.2\%$ decoding latency gain with respect to fast SC and SCL decoding algorithms, respectively, and up to $63.6\%$ and $49.8\%$ if a performance loss is accepted, whose amount depends on code and decoding algorithm parameters, along with the desired speedup.

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arXiv2020

Operation Merging for Hardware Implementations of Fast Polar Decoders

Polar codes are a class of linear block codes that provably achieves channel capacity. They have been selected as a coding scheme for the control channel of enhanced mobile broadband (eMBB) scenario for $5^{\text{th}}$ generation wireless communication networks (5G) and are being considered for additional use scenarios. As a result, fast decoding techniques for polar codes are essential. Previous works targeting improved throughput for successive-cancellation (SC) decoding of polar codes are semi-parallel implementations that exploit special maximum-likelihood (ML) nodes. In this work, we present a new fast simplified SC (Fast-SSC) decoder architecture. Compared to a baseline Fast-SSC decoder, our solution is able to reduce the memory requirements. We achieve this through a more efficient memory utilization, which also enables to execute multiple operations in a single clock cycle. Finally, we propose new special node merging techniques that improve the throughput further, and detail a new Fast-SSC-based decoder architecture to support merged operations. The proposed decoder reduces the operation sequence requirement by up to $39\%$, which enables to reduce the number of time steps to decode a codeword by $35\%$. ASIC implementation results with 65 nm TSMC technology show that the proposed decoder has a throughput improvement of up to $31\%$ compared to previous Fast-SSC decoder architectures.

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arXiv2020

Fast-SCAN decoding of Polar Codes

Polar codes are able to achieve the capacity of memoryless channels under successive cancellation (SC) decoding. Soft Cancellation (SCAN) is a soft-output decoder based on the SC schedule, useful in iterative decoding and concatenation of polar codes. However, the sequential nature of this decoder leads to high decoding latency compared to state-of-the-art codes. To reduce the latency of SCAN, in this paper we identify special nodes in the decoding tree, corresponding to specific frozen-bit sequences, and propose dedicated low-latency decoding approaches for each of them. The resulting fast-SCAN decoder does not alter the soft-output compared to the standard SCAN while dramatically reducing the decoding latency and yielding the same error-correction performance.

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arXiv2020

SCAN List Decoding of Polar Codes

In this paper we propose an enhanced soft cancellation (SCAN) decoder for polar codes based on decoding stages permutation. The proposed soft cancellation list (SCANL) decoder runs $L$ independent SCAN decoders, each one relying on a different permuted factor graph. The estimated bits are selected among the $L$ candidates through a dedicated metric provided by the decoders. Furthermore, we introduce an early-termination scheme reducing decoding latency without affecting error correction performance. We investigate the error-correction performance of the proposed scheme under various combinations of number of iterations used, permutation set and early-termination condition. Simulation results show that the proposed SCANL provides similar results when compared with belief propagation list, while having a smaller complexity. Moreover, for large list sizes, SCANL outperforms non-CRC aided successive cancellation list decoding.

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arXiv2020

On List Decoding of 5G-NR Polar Codes

The 5th generation wireless systems (5G) standardization process of the 3rd generation partnership project (3GPP) chose polar codes as a channel coding scheme for the control channel. In case of downlink control information, polar codes are concatenated with distributed distributed cyclic redundancy check (CRC). Whereas CRC bits allow to improve the performance of successive cancellation list (SCL) decoders by improving distance properties, distributed CRC bits allow for path pruning and decoding early-termination. In this paper, we show how to take advantage of the distributed CRC to improve SCL decoding, analyzing various schemes having different earlytermination and error correction properties. Simulation results compare the proposed decoding schemes, showing different tradeoffs between error-correction performance and early-termination with different decoder parameters.

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arXiv2020

Design of Polar Codes in 5G New Radio

Polar codes have attracted the attention of academia and industry alike in the past decade, such that the 5$^\text{th}$ generation wireless systems (5G) standardization process of the 3$^\text{th}$ generation partnership project (3GPP) chose polar codes as a channel coding scheme. In this tutorial, we provide a description of the encoding process of polar codes adopted by the 5G standard. We illustrate the struggles of designing a family of polar codes able to satisfy the demands of 5G systems, with particular attention to rate flexibility and low decoding latency. The result of these efforts is an elaborate framework that applies novel coding techniques to provide a solid channel code for NR requirements.

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arXiv2019

Practical Product Code Construction of Polar Codes

In this paper, we study the connection between polar codes and product codes. Our analysis shows that the product of two polar codes is again a polar code, and we provide guidelines to compute its frozen set on the basis of the frozen sets of the component polar codes. Moreover, we show how polar codes can be described as irregular product codes. We propose a two-step decoder for long polar codes taking advantage of this dual nature to heavily reduce decoding latency. Finally, we show that the proposed decoding technique outperforms both standard polar codes and state-of-the-art codes for optical communications under latency constraints.

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arXiv2019

Rate-Flexible Fast Polar Decoders

Polar codes have gained extensive attention during the past few years and recently they have been selected for the next generation of wireless communications standards (5G). Successive-cancellation-based (SC-based) decoders, such as SC list (SCL) and SC flip (SCF), provide a reasonable error performance for polar codes at the cost of low decoding speed. Fast SC-based decoders, such as Fast-SSC, Fast-SSCL, and Fast-SSCF, identify the special constituent codes in a polar code graph off-line, produce a list of operations, store the list in memory, and feed the list to the decoder to decode the constituent codes in order efficiently, thus increasing the decoding speed. However, the list of operations is dependent on the code rate and as the rate changes, a new list is produced, making fast SC-based decoders not rate-flexible. In this paper, we propose a completely rate-flexible fast SC-based decoder by creating the list of operations directly in hardware, with low implementation complexity. We further propose a hardware architecture implementing the proposed method and show that the area occupation of the rate-flexible fast SC-based decoder in this paper is only $38\%$ of the total area of the memory-based base-line decoder when 5G code rates are supported.

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arXiv2019

Construction and Decoding of Product Codes with Non-Systematic Polar Codes

Product codes are widespread in optical communications, thanks to their high throughput and good error-correction performance. Systematic polar codes have been recently considered as component codes for product codes. In this paper, we present a novel construction for product polar codes based on non-systematic polar codes. We prove that the resulting product code is actually a polar code, having a frozen set that is dependent on the frozen sets of the component polar codes. We propose a low-complexity decoding algorithm exploiting the dual nature of the constructed code. Performance analysis and simulations show high decoding speed, that allows to construct long codes while maintaining low decoding latency. The resulting high throughput and good error-correction performance are appealing for optical communication systems and other systems where high throughput and low latency are required.

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arXiv2018

Partitioned Successive-Cancellation Flip Decoding of Polar Codes

Polar codes are a class of channel capacity achieving codes that has been selected for the next generation of wireless communication standards. Successive-cancellation (SC) is the first proposed decoding algorithm, suffering from mediocre error-correction performance at moderate code length. In order to improve the error-correction performance of SC, two approaches are available: (i) SC-List decoding which keeps a list of candidates by running a number of SC decoders in parallel, thus increasing the implementation complexity, and (ii) SC-Flip decoding that relies on a single SC module, and keeps the computational complexity close to SC. In this work, we propose the partitioned SC-Flip (PSCF) decoding algorithm, which outperforms SC-Flip in terms of error-correction performance and average computational complexity, leading to higher throughput and reduced energy consumption per codeword. We also introduce a partitioning scheme that best suits our PSCF decoder. Simulation results show that at equivalent frame error rate, PSCF has up to $5 \times$ less computational complexity than the SC-Flip decoder. At equivalent average number of iterations, the error-correction performance of PSCF outperforms SC-Flip by up to $0.15$ dB at frame error rate of $10^{-3}$.

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