arXiv subjects

Carmen G. Almudever

Publications and source records attributed to Carmen G. Almudever.

At least 19 recordsLinked to original sources

arXiv2026

An Analytical Approach to Design Space Exploration for Cavity-Mediated Quantum State Transfer in Multi-core Architectures

In multi-core quantum computing architectures, waveguide-mediated interconnects are essential for facilitating fast, high-fidelity quantum state transfer between qubits located in different chips. However, optimizing these systems typically relies on computationally expensive numerical simulations that offer limited physical insight. In this work, we derive exact analytical expressions for the state transfer dynamics of a two-qubit system coupled via a waveguide, modeled through a Jaynes-Cummings Hamiltonian and the Lindblad master equation. We apply the Monte Carlo wave-function method and obtain a closed-form solution for qubit occupation probabilities that accounts for both detuning and dissipative losses. Our analytical framework provides a significant computational speedup compared to standard numerical solvers, enabling large-scale parameter sweeps while maintaining high precision in both fidelity and latency predictions. Furthermore, the model reveals and explains systematic low-fidelity regions arising from destructive interference between internal oscillations and detuning-induced envelopes, which are phenomena that are difficult to characterize through numerical means alone. Finally, we propose a simplified latency model and an efficiency-based function to enable rapid identification of optimal operating points. This analytical approach provides a robust foundation for the design and optimization of interconnects in multi-core quantum processors.

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arXiv2026

Adaptive Parallelism-Aware Qubit Routing for Ion Trap QCCD Architectures

Trapped-ion Quantum Charge-Coupled Device (QCCD) architectures promise scalability through interconnected trap zones and dynamic ion transport; however, this transport capability creates a complex compilation challenge: how to move qubits efficiently without degrading fidelity. We introduce a routing strategy that turns this challenge into an advantage by exploiting operational parallelism across traps while adapting to both algorithmic structure and device topology through a configurable multi-parameter scoring mechanism. Across a broad suite of benchmarks and QCCD layouts, the method consistently reduces ion-transport overhead and improves execution fidelity, outperforming state-of-the-art routing techniques. These results highlight that explicitly balancing movement overhead and execution parallelism under architectural constraints is key to unlocking the full potential of modular trapped-ion quantum processors.

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arXiv2026

Assessing the Impact of Low Resolution Control Electronics on Quantum Neural Network Performance

Scaling quantum computers requires tight integration of cryogenic control electronics with quantum processors, where Digital-to-Analog Converters (DACs) face severe power and area constraints. We investigate quantum neural network (QNN) training and inference under finite DAC resolution constraints, evaluating two QNN architectures across four diverse datasets (MNIST, Fashion-MNIST, Iris, Breast Cancer). Pre-trained QNNs achieve accuracy nearly indistinguishable from infinite-precision baselines when deployed on quantum systems with 6-bit DAC control electronics, exhibiting characteristic elbow curves with diminishing returns beyond 3-5 bits depending on the dataset. However, training QNNs directly under quantization constraints reveals gradient deadlock below 12-bit resolution, where parameter updates fall below quantization step sizes, preventing training entirely. We introduce temperature-controlled stochastic quantization that overcomes this limitation through probabilistic parameter updates, enabling successful training at 4-10 bit resolutions. Remarkably, stochastic quantization not only matches but frequently exceeds infinite-precision baseline performance across both architectures and all datasets. Our findings demonstrate that low-resolution control electronics (4-10 bits) need not compromise QML performance while enabling substantial power and area reduction in cryogenic control systems, presenting significant implications for practical quantum hardware scaling and hardware-software co-design of QML systems.

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arXiv2026

Exponential improvement in benchmarking multiphoton interference

Several photonic quantum technologies rely on the ability to generate multiple indistinguishable photons. Benchmarking the level of indistinguishability of these photons is essential for scalability. The Hong-Ou-Mandel dip provides a benchmark for the indistinguishability between two photons, and extending this test to the multi-photon setting has so far resulted in a protocol that computes the genuine n-photon indistinguishability (GI). However, this protocol has a sample complexity that increases exponentially with the number of input photons for an estimation of GI up to a given additive error. To address this problem, we introduce new theorems that strengthen our understanding of the relationship between distinguishability and the suppression laws of the quantum Fourier transform interferometer (QFT). Building on this, we propose a protocol using the QFT for benchmarking GI that achieves constant sample complexity for the estimation of GI up to a given additive error for prime photon numbers, and sub-polynomial scaling otherwise, representing an exponential improvement over the state of the art. We prove the optimality of our protocol in many relevant scenarios and validate our approach experimentally on Quandela's reconfigurable photonic quantum processor, where we observe a clear advantage in runtime and precision over the state of the art. We therefore establish the first scalable method for computing multi-photon indistinguishability, which applies naturally to current and near-term photonic quantum hardware.

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arXiv2025

Enabling Technologies for Scalable Superconducting Quantum Computing

Experiments with superconducting quantum processors have successfully demonstrated the basic functions needed for quantum computation and evidence of utility, albeit without a sizable array of error-corrected qubits. The realization of the full potential of quantum computing centers on achieving large scale fault-tolerant quantum computers. Science, engineering and industry advances are needed to robustly generate, sustain, and efficiently manipulate an exponentially large computational (Hilbert) space as well as supply the number and quality components needed for such a scaled system. In this article, we suggest critical areas of quantum system and ecosystem development, with respect to the handling and transmission of quantum information within and out of a cryogenic environment, that would accelerate the development of quantum computers based on superconducting circuits.

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arXiv2025

Lattice Surgery Aware Resource Analysis for the Mapping and Scheduling of Quantum Circuits for Scalable Modular Architectures

Quantum computing platforms are evolving to a point where placing high numbers of qubits into a single core comes with certain difficulties such as fidelity, crosstalk, and high power consumption of dense classical electronics. Utilizing distributed cores, each hosting logical data qubits and logical ancillas connected via classical and quantum communication channels, offers a promising alternative. However, building such a system for logical qubits requires additional optimizations, such as minimizing the amount of state transfer between cores for inter-core two-qubit gates and optimizing the routing of magic states distilled in a magic state factory. In this work, we investigate such a system and its statistics in terms of classical and quantum resources. First, we restrict our quantum gate set to a universal gate set consisting of CNOT, H, T, S, and Pauli gates. We then developed a framework that can take any quantum circuit, transpile it to our gate set using Qiskit, and then partition the qubits using the KaHIP graph partitioner to balanced partitions. Afterwards, we built an algorithm to map these graphs onto the 2D mesh of quantum cores by converting the problem into a Quadratic Assignment Problem with Fixed Assignment (QAPFA) to minimize the routing of leftover two-qubit gates between cores and the total travel of magic states from the magic state factory. Following this stage, the gates are scheduled using an algorithm that takes care of the timing of the gate set. As a final stage, our framework reports detailed statistics such as the number of classical communications, the number of EPR pairs and magic states consumed, and timing overheads for pre- and post- processing for inter-core state transfers. These results help to quantify both classical and quantum resources that are used in distributed logical quantum computing architectures.

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arXiv2025

Characterizing Scaling Trends of Post-Compilation Circuit Resources for NISQ-era QML Models

This work investigates the scaling characteristics of post-compilation circuit resources for Quantum Machine Learning (QML) models on connectivity-constrained NISQ processors. We analyze Quantum Kernel Methods and Quantum Neural Networks across processor topologies (linear, ring, grid, star), focusing on SWAP overhead, circuit depth, and two-qubit gate count. Our findings reveal that entangling strategy significantly impacts resource scaling, with circular and shifted circular alternating strategies showing steepest scaling. Ring topology demonstrates slowest resource scaling for most QML models, while Tree Tensor Networks lose their logarithmic depth advantage after compilation. Through fidelity analysis under realistic noise models, we establish quantitative relationships between hardware improvements and maximum reliable qubit counts, providing crucial insights for hardware-aware QML model design across the full-stack architecture.

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arXiv2025

Stacking the Odds: Full-Stack Quantum System Design Space Exploration

Design space exploration (DSE) plays an important role in optimising quantum circuit execution by systematically evaluating different configurations of compilation strategies and hardware settings. In this work, we study the impact of layout methods, qubit routing techniques, compiler optimization levels, and hardware-specific properties, including noise characteristics, topological structures, connectivity densities, and device sizes. By traversing these dimensions, we aim to understand how compilation choices interact with hardware features. A central question in our study is whether carefully selected device parameters and mapping strategies, including initial layouts and routing heuristics, can mitigate hardware-induced errors beyond standard error mitigation methods. Our results show that choosing the right software strategies (e.g., layout and routing) and tailoring hardware properties (e.g., reducing noise or leveraging connectivity) significantly enhances the fidelity of quantum circuit executions. We provide performance estimates using metrics such as circuit depth, gate count, and expected fidelity. These findings highlight the value of hardware-software co-design, especially as quantum systems scale and move toward error-corrected computing. Our simulations, though noisy, include quantum error correction (QEC) scenarios, revealing similar sensitivities to layout and connectivity. This suggests that co-design principles will be vital for integrating QEC in future devices. Overall, we offer practical guidance for co-optimizing mapping, routing, and hardware configuration in real-world quantum computing.

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arXiv2025

Waveguide QED Analysis of Quantum-Coherent Links for Modular Quantum Computing

Waveguides potentially offer an effective medium for interconnecting quantum processors within a modular framework, facilitating the coherent quantum state transfer between the qubits across separate chips. In this work, we analyze a quantum communication scenario where two qubits are connected to a shared waveguide, whose resonance frequency may match or not match that of the qubits. Both configurations are simulated from the perspective of quantum electrodynamics (QED) to assess the system behavior and key factors that influence reliable inter-chip communication. The primary performance metrics analyzed are quantum state transfer fidelity and latency, considering the impact of key system parameters such as the qubit-waveguide detuning, coupling strength, waveguide decay rate, and qubit decay rate. We present the system design requirements that yield enhanced state transmission fidelity rates and lowered latency, and discuss the scalability of waveguide-mediated interconnects considering various configurations of the system.

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arXiv2025

ArtA: Automating Design Space Exploration of Spin Qubit Architectures

In the fast-paced field of quantum computing, identifying the architectural characteristics that will enable quantum processors to achieve high performance across a diverse range of quantum algorithms continues to pose a significant challenge. Given the extensive and costly nature of experimentally testing different designs, this paper introduces the first Design Space Exploration (DSE) for quantum-dot spin-qubit architectures. Utilizing the upgraded SpinQ compilation framework, this study explores a substantial design space comprising 29,312 spin-qubit-based architectures and applies an innovative optimization tool, ArtA (Artificial Architect), to speed up the design space traversal. ArtA can leverage 17 optimization configurations, significantly reducing exploration times by up to 99.1% compared to a traditional brute-force approach while maintaining the same result quality. After a comprehensive evaluation of best-matching optimization configurations per quantum circuit, ArtA suggests specific as well as universal architectural features that provide optimal performance across the examined circuits. Our work demonstrates that combining DSE methodologies with optimization algorithms can be effectively used to generate meaningful design insights for quantum processor development.

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arXiv2025

Exploring operation parallelism vs. ion movement in ion-trapped QCCD architectures

Ion-trapped Quantum Charge-Coupled Device (QCCD) architectures have emerged as a promising alternative to scale single-trap devices by interconnecting multiple traps through ion shuttling, enabling the execution of parallel operations across different traps. While this parallelism enhances computational throughput, it introduces additional operations, raising the following question: do the benefits of parallelism outweigh the potential loss of fidelity due to increased ion movements? This paper answers this question by exploring the trade-off between the parallelism of operations and fidelity loss due to movement overhead, comparing sequential execution in single-trap devices with parallel execution in QCCD architectures. We first analyze the fidelity impact of both methods, establishing the optimal number of ion movements for the worst-case scenario. Next, we evaluate several quantum algorithms on QCCD architectures by exploiting parallelism through ion distribution across multiple traps. This analysis identifies the algorithms that benefit the most from parallel executions, explores the underlying reasons, and determines the optimal balance between movement overhead and fidelity loss for each algorithm.

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arXiv2024

Lightcone Bounds for Quantum Circuit Mapping via Uncomplexity

Efficiently mapping quantum circuits onto hardware is an integral part of the quantum compilation process, wherein a circuit is modified in accordance with the stringent architectural demands of a quantum processor. Many techniques exist for solving the quantum circuit mapping problem, in addition to several theoretical perspectives that relate quantum circuit mapping to problems in classical computer science. This work considers a novel perspective on quantum circuit mapping, in which the routing process of a simplified circuit is viewed as a composition of quantum operations acting on density matrices representing the quantum circuit and processor. Drawing on insight from recent advances in quantum circuit complexity and information geometry, we show that a minimal SWAP-gate count for executing a quantum circuit on a device emerges via the minimization of the distance between quantum states using the quantum Jensen-Shannon divergence, which we dub the lightcone bound. Additionally, we develop a novel initial placement algorithm based on a graph similarity search that selects the partition nearest to a graph isomorphism between interaction and coupling graphs. From these two ingredients, we construct an algorithm for calculating the lightcone bound, which is directly compared alongside the IBM Qiskit compiler for over $600$ realistic benchmark experiments, as well as against a brute-force method for smaller benchmarks. In our simulations, we unambiguously find that neither the brute-force method nor the Qiskit compiler surpasses our bound, signaling utility for estimating minimal overhead when realizing quantum algorithms on constrained quantum hardware. This work also constitutes the first use of quantum circuit uncomplexity to practically-relevant quantum computing. We anticipate that this method may have diverse applicability outside of the scope of quantum information science.

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arXiv2024

Scaling and assigning resources on ion trap QCCD architectures

Ion trap technologies have earned significant attention as potential candidates for quantum information processing due to their long decoherence times and precise manipulation of individual qubits, distinguishing them from other candidates in the field of quantum technologies. However, scalability remains a challenge, as introducing additional qubits into a trap increases noise and heating effects, consequently decreasing operational fidelity. Trapped-ion Quantum Charge-Coupled Device (QCCD) architectures have addressed this limitation by interconnecting multiple traps and employing ion shuttling mechanisms to transfer ions among traps. This new architectural design requires the development of novel compilation techniques for quantum algorithms, which efficiently allocate and route qubits, and schedule operations. The aim of a compiler is to minimize ion movements and, therefore, reduce the execution time of the circuit to achieve a higher fidelity. In this paper, we propose a novel approach for initial qubit placement, demonstrating enhancements of up to 50\% compared to prior methods. Furthermore, we conduct a scalability analysis on two distinct QCCD topologies: a 1D-linear array and a ring structure. Additionally, we evaluate the impact of the excess capacity -- i.e. the number of free spaces within a trap -- on the algorithm performance.

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arXiv2024

On the use of calibration data in error-aware compilation techniques for NISQ devices

Reliably executing quantum algorithms on noisy intermediate-scale quantum (NISQ) devices is challenging, as they are severely constrained and prone to errors. Efficient quantum circuit compilation techniques are therefore crucial for overcoming their limitations and dealing with their high error rates. These techniques consider the quantum hardware restrictions, such as the limited qubit connectivity, and perform some transformations to the original circuit that can be executed on a given quantum processor. Certain compilation methods use error information based on calibration data to further improve the success probability or the fidelity of the circuit to be run. However, it is uncertain to what extent incorporating calibration information in the compilation process can enhance the circuit performance. For instance, considering the most recent error data provided by vendors after calibrating the processor might not be functional enough as quantum systems are subject to drift, making the latest calibration data obsolete within minutes. In this paper, we explore how different usage of calibration data impacts the circuit fidelity, by using several compilation techniques and quantum processors (IBM Perth and Brisbane). To this aim, we implemented a framework that incorporates some of the state-of-the-art noise-aware and non-noise-aware compilation techniques and allows the user to perform fair comparisons under similar processor conditions. Our experiments yield valuable insights into the effects of noise-aware methodologies and the employment of calibration data. The main finding is that pre-processing historical calibration data can improve fidelity when real-time calibration data is not available due to factors such as cloud service latency and waiting queues between compilation and execution on the quantum backend.

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arXiv2024

Benchmarking Emerging Cavity-Mediated Quantum Interconnect Technologies for Modular Quantum Computers

Modularity is a promising approach for scaling up quantum computers and therefore integrating higher qubit counts. The essence of such architectures lies in their reliance on high-fidelity and fast quantum state transfers enabled by generating entanglement between chips. In addressing the challenge of implementing quantum coherent communication channels to interconnect quantum processors, various techniques have been proposed to account for qubit technology specifications and the implemented communication protocol. By employing Design Space Exploration (DSE) methodologies, this work presents a comparative analysis of the cavity-mediated interconnect technologies according to a defined figure of merit, and we identify the configurations related to the cavity and atomic decay rates as well as the qubit-cavity coupling strength that meet the efficiency thresholds. We therefore contribute to benchmarking contemporary cavity-mediated quantum interconnects and guide the development of reliable and scalable chip-to-chip links for modular quantum computers.

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arXiv2024

Profiling quantum circuits for their efficient execution on single- and multi-core architectures

Application-specific quantum computers offer the most efficient means to tackle problems intractable by classical computers. Realizing these architectures necessitates a deep understanding of quantum circuit properties and their relationship to execution outcomes on quantum devices. Our study aims to perform for the first time a rigorous examination of quantum circuits by introducing graph theory-based metrics extracted from their qubit interaction graph and gate dependency graph alongside conventional parameters describing the circuit itself. This methodology facilitates a comprehensive analysis and clustering of quantum circuits. Furthermore, it uncovers a connection between parameters rooted in both qubit interaction and gate dependency graphs, and the performance metrics for quantum circuit mapping, across a range of established quantum device and mapping configurations. Among the various device configurations, we particularly emphasize modular (i.e., multi-core) quantum computing architectures due to their high potential as a viable solution for quantum device scalability. This thorough analysis will help us to: i) identify key attributes of quantum circuits that affect the quantum circuit mapping performance metrics; ii) predict the performance on a specific chip for similar circuit structures; iii) determine preferable combinations of mapping techniques and hardware setups for specific circuits; and iv) define representative benchmark sets by clustering similarly structured circuits.

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arXiv2024

beSnake: A routing algorithm for scalable spin-qubit architectures

As quantum computing devices increase in size with respect to the number of qubits, two-qubit interactions become more challenging, necessitating innovative and scalable qubit routing solutions. In this work, we introduce beSnake, a novel algorithm specifically designed to address the intricate qubit routing challenges in scalable spin-qubit architectures. Unlike traditional methods in superconducting architectures that solely rely on SWAP operations, beSnake also incorporates the shuttle operation to optimize the execution time and fidelity of quantum circuits and achieves fast computation times of the routing task itself. Employing a simple breadth-first search approach, beSnake effectively manages the restrictions created by diverse topologies and qubit positions acting as obstacles, for up to 72\% qubit density. It also has the option to adjust the level of optimization and to dynamically tackle parallelized routing tasks, all the while maintaining noise awareness. Our simulations demonstrate beSnake's advantage over an existing routing solution on random circuits and real quantum algorithms with up to $1,000$ qubits, showing an average improvement of up to $80\%$ in gate overhead and $54\%$ in depth overhead, and up to $8.33$ times faster routing times.

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arXiv2024

SpinQ: Compilation strategies for scalable spin-qubit architectures

Despite NISQ devices being severely constrained, hardware- and algorithm-aware quantum circuit mapping techniques have been developed to enable successful algorithm executions. Not so much attention has been paid to mapping and compilation implementations for spin-qubit quantum processors due to the scarce availability of experimental devices and their small sizes. However, based on their high scalability potential and their rapid progress it is timely to start exploring solutions on such devices. In this work, we discuss the unique mapping challenges of a scalable crossbar architecture with shared control and introduce SpinQ, the first native compilation framework for scalable spin-qubit architectures. At the core of SpinQ is the Integrated Strategy that addresses the unique operational constraints of the crossbar while considering compilation scalability and obtaining a O(n) computational complexity. To evaluate the performance of SpinQ on this novel architecture, we compiled a broad set of well-defined quantum circuits and performed an in-depth analysis based on multiple metrics such as gate overhead, depth overhead, and estimated success probability, which in turn allowed us to create unique mapping and architectural insights. Finally, we propose novel mapping techniques that could increase algorithm success rates on this architecture and potentially inspire further research on quantum circuit mapping for other scalable spin-qubit architectures.

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