Carter Antley | Searcharxiv

arXiv2026

Generalized Nordhaus--Gaddum Inequalities for Eigenvalues

For a graph $G$, let $ \lambda_1(G)\ge \lambda_2(G)\ge \cdots \ge \lambda_n(G)$ denote the adjacency eigenvalues of $G$. We investigate the asymptotic maximum of \[ \lambda_i(G)+\lambda_j(\overline G) \] for fixed $i$ and $j$. We prove general bounds on $\lambda_i(G) + \lambda_{j}(\overline{G})$ for all pairs $(i, j)$ and also give general bounds on the related problem of minimizing $\lambda_{n-i+1}(G) + \lambda_{n-j+1}(\overline{G})$ for fixed $i$ and $j$. We prove that for all looped graphs $G$ on $n$ vertices, \[\lambda_1(G) + \lambda_2(\overline{G}) \le \frac87 n. \] Our method also gives a new short proof of the Nordhaus-Gaddum result for the spectral radius proved by Terpai that $\lambda_1(G) + \lambda_1(\overline{G}) \le \frac43n - 1$. We also show the close relation of these Nordhaus-Gaddum type problems to recent work on the maximum spectral gaps of graphs by Brooks, Linz and Lu.

math.CO↗

arXiv2026

Hardware-Accelerated Line-Rate Bitstream Screening for Secure FPGA Reconfiguration

As Field-Programmable Gate Arrays (FPGAs) scale in multi-tenant cloud and edge-AI environments, the configuration bitstream has become a critical, yet opaque, security boundary. Existing hardware Trojan detection methods often rely on trusted design artifacts or computationally intensive reverse-engineering, introducing prohibitive latencies in dynamic, "just-in-time" reconfiguration workflows. This paper presents BLADEI (Bitstream-Level Abnormality Detection for Embedded Inference), a bitstream-level security framework designed for deployment-time screening of FPGA configurations without requiring source code, netlists, or vendor-specific tooling. BLADEI introduces a hybrid architecture that combines multi-scale byte-sequence learning with compact statistical representations to detect anomalous configurations directly from raw bitstreams. We implement the framework on a Xilinx PYNQ-Z1 system, demonstrating an end-to-end cloud-to-edge pipeline that enforces security prior to FPGA configuration. Evaluating across 1,383 bitstreams, BLADEI achieves a macro F1-score of 0.91. However, our systems-level characterization reveals a "preprocessing wall": software-based feature extraction accounts for 92% of the total 16.4-second latency, while model inference requires only 1.4 seconds. To address this bottleneck, we propose a streaming hardware-accelerated feature extraction engine designed for the FPGA programmable logic (PL). The evaluation shows that PL-based streaming engine can reduce feature-extraction latency to the millisecond range. This work positions bitstream-level screening as a first-class primitive and demonstrates that hardware-accelerated preprocessing is the key enabler for securing next-generation reconfigurable custom computing machines at line rate.

cs.CR↗