Chandra Gandu | Searcharxiv

arXiv2026

Formal Foundations for Known Good Reliable Die Screening in Chiplet-Based AI Systems-on-Chip

The rapid growth of chiplet-based artificial intelligence systems-on-chip (SoCs) has exposed a fundamental gap in semiconductor test methodology. Existing Known Good Die (KGD) screening guarantees pre-assembly functional correctness, yet it offers no probabilistic assurance of post-assembly reliability lifetime. To address this limitation, the present work formalizes the transition from KGD to Known Good Reliable Die (KGRD) screening as a constrained inference problem over incomplete pre-assembly observability. Building upon this formulation, four interlocking contributions are presented: (i) a Bayesian probabilistic risk model that maps pre-assembly telemetry to post-assembly failure likelihood with a quantified observability bias bound; (ii) a safety-gated decision architecture that provides a provable post-assembly failure probability guarantee; (iii) uncertainty-aware disposition boundaries derived from Bayes-optimal decision theory; and (iv) a constrained closed-loop feedback mechanism that delivers consistent model improvement without violating reliability constraints. A Monte Carlo simulation study on N = 4,000 synthetic dies verifies all four theoretical properties and confirms that the safety guarantee holds uniformly across the full range of tested gate threshold.

cs.AR↗

arXiv2026

A Theoretical Framework for Stochastic Activity Prediction in Tensor Accelerator Wallace-Tree Multipliers

Tensor accelerator multipliers burn dynamic power on every clock cycle, even when sparse operands require very little internal switching. No existing technique addresses this: zero-detection requires exactly-zero operands, structural power gating requires an idle multiplier, and offline weight selection cannot respond to runtime data. This paper introduces Stochastic Activity Prediction (SAP), which closes this gap by examining the Hamming weight of arriving operands before the multiplier executes, predicting low switching activity, and freezing the inputs when a deterministic Safety Controller independently confirms the reuse is correct. Mispredictions cause missed savings, never wrong answers. Three formal results underpin SAP: (i) a Spectral Contraction Lemma proving that Wallace-tree activity depends on operand bit density, not bit position, establishing Lipschitz constant $L\phi = 3/2$ and prediction error below $10^{-13}$ for a 256-cycle window; (ii) an Information Retention Theorem showing $\eta_I \ge 1 - O(\log n/n)$, so one bit per cycle captures nearly all predictive information about $O(n^2)$ internal nodes; and (iii) a Bernoulli Optimality Theorem proving the chosen encoding is shown to be optimal, within the family of calibrated one-bit encoders of Hamming-weight statistics considered. SAP addresses the specific layer of the tensor accelerator power stack that existing techniques do not cover.

cs.AR↗