arXiv subjects

Chankeun Yoon

Publications and source records attributed to Chankeun Yoon.

3 recordsLinked to original sources

arXiv2026

Physical Basis for Band Transport and Dimensionality in Amorphous Oxide Semiconductor Field-Effect Transistors

A consistent and widely accepted physical basis for interpretation of charge transport in amorphous oxide semiconductor (AOS) field-effect transistors (FETs), and more generally device physics, has been hampered by uncertainties in crystalline order, dimensionality, and the effects of a significant density of traps. The overarching theme of this paper is to build and justify a much-needed conceptual framework for describing advanced AOS transistors, particularly those with very small channel lengths. Combining new work and selecting prior research results on charge transport and device physics together with literature reports from various groups on morphology, physical properties, electronic structure and percolation effects, the main evidence that is available in support of a trap-influenced band transport picture in quasi-2-dimensional channels in high mobility AOS FETs is presented.

cond-mat.mtrl-sci↗

arXiv2026

Velocity-field characteristics and device performance in nanoscale amorphous oxide Thin-Film-Transistors

The electron velocity-electric field characteristics in short channel length (50-100 nm) amorphous oxide field-effect transistors (FETs) are described using measured experimental data from indium gallium zinc oxide (IGZO) FETs in conjunction with a physics-based model. Such understanding is crucial for the design of FETs for emerging applications such as in back-end-of-line circuitry for advanced memories and artificial intelligence hardware. In such semiconductor systems, there is an interplay between trapping and extended state (band) transport that has to be considered in detail for a more complete physical understanding of device operation. The approach described in this paper demonstrates such a method and its use for an exemplary semiconductor IGZO. It can be used in many emerging thin-film semiconductors, including several amorphous oxide semiconductors. The carrier mobility is calculated for dominant scattering mechanisms such as trapped carrier scattering and optical phonon scattering. The carrier velocity is computed from the mobility using a modified Caughey-Thomas equation. The physical model considers contact resistance, Joule heating, and electric-field-induced carrier heating, all of which are very important in small geometry FETs. The carrier velocity exhibits a tendency to saturate at high electric fields and reaches values > 2*10^6 cm/s when averaged over all induced carriers (both trapped and in the band) and > 4*10^6 cm/s for carriers in the band.

cond-mat.mtrl-sci↗

arXiv2025

Enhancing Gate Control and Mitigating Short Channel Effects in 20-50 nm Channel Length Amorphous Oxide Thin Film Transistors

Field-effect transistors (FETs) with single gates are adversely affected by short channel effects such as drain-induced barrier lowering (DIBL) and increases in the magnitude of sub-threshold swing as the channel length is reduced. Dual-gate and gate-all-around geometries are often employed to improve gate control in very short channel length transistors. This can introduce significant process complexity to the device fabrication compared to single-gate transistors. It is shown in this paper that substantial reductions in short channel effects are possible in single-gate field-effect transistors with indium gallium zinc oxide semiconductor channels by modifying the design of the source and drain electrodes to possess an array of tapered tips which are designated as nanospike electrodes. 20-25 nm channel length FETs with nanospike electrodes have DIBL and other key metrics that are comparable to those in much larger (70-80 nm) channel length FETs with a conventional source/drain electrode design. These improvements stem from better gate control near the source and drain electrode tips due to the shape of these electrodes. These bottom gate FETs had a gate insulator consisting of 9 nm thick Al2O3 and independent Ni gates. This design approach is expected to be very helpful for a variety of semiconductor technologies being considered for back-end-of-line (BEOL) applications.

cond-mat.mtrl-sci↗