arXiv subjects

Chenming Hu

Publications and source records attributed to Chenming Hu.

10 recordsLinked to original sources

arXiv2025

Physics-Informed Neural Networks for Device and Circuit Modeling: A Case Study of NeuroSPICE

We present NeuroSPICE, a physics-informed neural network (PINN) framework for device and circuit simulation. Unlike conventional SPICE, which relies on time-discretized numerical solvers, NeuroSPICE leverages PINNs to solve circuit differential-algebraic equations (DAEs) by minimizing the residual of the equations through backpropagation. It models device and circuit waveforms using analytical equations in time domain with exact temporal derivatives. While PINNs do not outperform SPICE in speed or accuracy during training, they offer unique advantages such as surrogate models for design optimization and inverse problems. NeuroSPICE's flexibility enables the simulation of emerging devices, including highly nonlinear systems such as ferroelectric memories.

cs.AI↗

arXiv2025

Optimal Brain Apoptosis

The increasing complexity and parameter count of Convolutional Neural Networks (CNNs) and Transformers pose challenges in terms of computational efficiency and resource demands. Pruning has been identified as an effective strategy to address these challenges by removing redundant elements such as neurons, channels, or connections, thereby enhancing computational efficiency without heavily compromising performance. This paper builds on the foundational work of Optimal Brain Damage (OBD) by advancing the methodology of parameter importance estimation using the Hessian matrix. Unlike previous approaches that rely on approximations, we introduce Optimal Brain Apoptosis (OBA), a novel pruning method that calculates the Hessian-vector product value directly for each parameter. By decomposing the Hessian matrix across network layers and identifying conditions under which inter-layer Hessian submatrices are non-zero, we propose a highly efficient technique for computing the second-order Taylor expansion of parameters. This approach allows for a more precise pruning process, particularly in the context of CNNs and Transformers, as validated in our experiments including VGG19, ResNet32, ResNet50, and ViT-B/16 on CIFAR10, CIFAR100 and Imagenet datasets. Our code is available at https://github.com/NEU-REAL/OBA.

cs.CV↗

arXiv2024

Fully Asynchronous Neuromorphic Perception for Mobile Robot Dodging with Loihi Chips

Sparse and asynchronous sensing and processing in natural organisms lead to ultra low-latency and energy-efficient perception. Event cameras, known as neuromorphic vision sensors, are designed to mimic these characteristics. However, fully utilizing the sparse and asynchronous event stream remains challenging. Influenced by the mature algorithms of standard cameras, most existing event-based algorithms still rely on the "group of events" processing paradigm (e.g., event frames, 3D voxels) when handling event streams. This paradigm encounters issues such as feature loss, event stacking, and high computational burden, which deviates from the intended purpose of event cameras. To address these issues, we propose a fully asynchronous neuromorphic paradigm that integrates event cameras, spiking networks, and neuromorphic processors (Intel Loihi). This paradigm can faithfully process each event asynchronously as it arrives, mimicking the spike-driven signal processing in biological brains. We compare the proposed paradigm with the existing "group of events" processing paradigm in detail on the real mobile robot dodging task. Experimental results show that our scheme exhibits better robustness than frame-based methods with different time windows and light conditions. Additionally, the energy consumption per inference of our scheme on the embedded Loihi processor is only 4.30% of that of the event spike tensor method on NVIDIA Jetson Orin NX with energy-saving mode, and 1.64% of that of the event frame method on the same neuromorphic processor. As far as we know, this is the first time that a fully asynchronous neuromorphic paradigm has been implemented for solving sequential tasks on real mobile robot.

cs.RO↗

arXiv2024

Spike-EVPR: Deep Spiking Residual Networks with SNN-Tailored Representations for Event-Based Visual Place Recognition

Event cameras are ideal for visual place recognition (VPR) in challenging environments due to their high temporal resolution and high dynamic range. However, existing methods convert sparse events into dense frame-like representations for Artificial Neural Networks (ANNs), ignoring event sparsity and incurring high computational cost. Spiking Neural Networks (SNNs) complement event data through discrete spike signals to enable energy-efficient VPR, but their application is hindered by the lack of effective spike-compatible representations and deep architectures capable of learning discriminative global descriptors. To address these limitations, we propose Spike-EVPR, a directly trained, end-to-end SNN framework tailored for event-based VPR. First, we introduce two complementary event representations, MCS-Tensor and TSS-Tensor, designed to reduce temporal redundancy while preserving essential spatio-temporal cues. Furthermore, we propose a deep spiking residual architecture that effectively aggregates these features to generate robust place descriptors. Extensive experiments on the Brisbane-Event-VPR and DDD20 datasets demonstrate that Spike-EVPR achieves state-of-the-art performance, improving Recall@1 by 7.61% and 13.20%, respectively, while significantly reducing energy consumption.

cs.CV↗

arXiv2023

EV-MGRFlowNet: Motion-Guided Recurrent Network for Unsupervised Event-based Optical Flow with Hybrid Motion-Compensation Loss

Event cameras offer promising properties, such as high temporal resolution and high dynamic range. These benefits have been utilized into many machine vision tasks, especially optical flow estimation. Currently, most existing event-based works use deep learning to estimate optical flow. However, their networks have not fully exploited prior hidden states and motion flows. Additionally, their supervision strategy has not fully leveraged the geometric constraints of event data to unlock the potential of networks. In this paper, we propose EV-MGRFlowNet, an unsupervised event-based optical flow estimation pipeline with motion-guided recurrent networks using a hybrid motion-compensation loss. First, we propose a feature-enhanced recurrent encoder network (FERE-Net) which fully utilizes prior hidden states to obtain multi-level motion features. Then, we propose a flow-guided decoder network (FGD-Net) to integrate prior motion flows. Finally, we design a hybrid motion-compensation loss (HMC-Loss) to strengthen geometric constraints for the more accurate alignment of events. Experimental results show that our method outperforms the current state-of-the-art (SOTA) method on the MVSEC dataset, with an average reduction of approximately 22.71% in average endpoint error (AEE). To our knowledge, our method ranks first among unsupervised learning-based methods.

cs.CV↗

arXiv2021

Ferroelectric HfO$_2$ Memory Transistors with High-$κ$ Interfacial Layer and Write Endurance Exceeding $10^{10}$ Cycles

We demonstrate ferroelectric (FE) memory transistors on a crystalline silicon channel with endurance exceeding $10^{10}$ cycles. The ferroelectric transistors (FeFETs) incorporate a high-$κ$ interfacial layer (IL) of thermally grown silicon nitride (SiN$_x$) and a thin 4.5 nm layer of Zr-doped FE-HfO$_2$ on a $\sim$30 nm SOI channel. The device shows a $\sim$ 1V memory window in a DC sweep of just $\pm$ 2.5V, and can be programmed and erased with voltage pulses of $V_G= \pm$ 3V at a pulse width of 250 ns. The device also shows very good retention behavior. These results indicate that appropriate engineering of the IL layer could substantially improve FeFET device performance and reliability.

physics.app-ph↗

arXiv2020

Negative Capacitance Enables FinFET Scaling Beyond 3nm Node

A comprehensive study of the scaling of negative capacitance FinFET (NC-FinFET) is conducted with TCAD. We show that the NC-FinFET can be scaled to "2.1nm node" and almost "1.5nm node" that comes two nodes after the industry "3nm node," which has 16nm Lg and is the last FinFET node according to the International Roadmap for Devices and Systems (IRDS). In addition, for the intervening nodes, NC-FinFET can meet IRDS Ion and Ioff target at target-beating VDD. The benefits of negative capacitance (NC) include improved subthreshold slope (SS), drain-induced barrier lowering (DIBL), Vt roll-off, transconductance over Id (Gm/Id), output conductance over Id (Gd/Id), and lower VDD. Further scaling may be achieved by improving capacitance matching between ferroelectric (FE) and dielectric (DE).

physics.app-ph↗

arXiv2020

Anomalous Subthreshold Behaviors in Negative Capacitance Transistors

Recent measurements on ultra-thin body Negative Capacitance Field Effect Transistors have shown subthreshold behaviors that are not expected in a classical MOSFET. Specifically, subthreshold swing was found to decrease with increased gate bias in the subthreshold region for devices measured over multiple gate lengths down to 30 nm. In addition, improvement in the subthreshold swing relative to control devices showed a non-monotonic dependence on the gate length. In this paper, using a Landau-Khanatnikov ferroelectric gate stack model calibrated with measured Capacitance-Voltage, we show that both these anomalous behaviors can be quantitatively reproduced with TCAD simulations.

physics.app-ph↗

arXiv2020

Compact Device Models for FinFET and Beyond

Compact device models play a significant role in connecting device technology and circuit design. BSIM-CMG and BSIM-IMG are industry standard compact models suited for the FinFET and UTBB technologies, respectively. Its surface potential based modeling framework and symmetry preserving properties make them suitable for both analog/RF and digital design. In the era of artificial intelligence / deep learning, compact models further enhanced our ability to explore RRAM and other NVM-based neuromorphic circuits. We have demonstrated simulation of RRAM neuromorphic circuits with Verilog-A based compact model at NCKU. Further abstraction with macromodels is performed to enable larger scale machine learning simulation.

cs.ET↗

arXiv2015

Single Crystal Functional Oxides on Silicon

Single crystalline thin films of complex oxides show a rich variety of functional properties such as ferroelectricity, piezoelectricity, ferro and antiferromagnetism etc. that have the potential for completely new electronic applications (1-2). Direct synthesis of such oxides on Si remains challenging due to the fundamental crystal chemistry and mechanical incompatibility of dissimilar interfaces (3-16). Here we report integration of thin (down to 1 unit cell) single crystalline, complex oxide films onto Si substrates, by epitaxial transfer at room temperature. In a field effect transistor using a transferred Pb0.2Zr0.8TiO3 (PZT) layer as the gate insulator, we demonstrate direct reversible control of the semiconductor channel charge with polarization state. These results represent the realization of long pursued but yet to be demonstrated single crystal functional oxides on-demand on silicon.

cond-mat.mtrl-sci↗