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Chong-Yuan Xu

Publications and source records attributed to Chong-Yuan Xu.

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Topological Codes from Space Groups: A Route beyond Translation Invariance

Translation invariance underlies all algebraic constructions of topological codes with geometrical locality. It has remained an open question whether codes that generically break this invariance can still be topological and simultaneously possess geometrical locality. Resolving this question is important both fundamentally---deepening our understanding of topological phases---and practically, as relaxing translation invariance could vastly expand the design space and potentially reduce resource overhead in fault-tolerant architectures. Here we introduce space-group codes, in which crystallographic point-group operations enter the bulk stabilizer algebra; bivariate bicycle (BB) codes arise as the translation-only limit. The key insight is that the point-group orbit resolves topology and locality together: it yields a computable algebraic criterion for topological order and a folded geometry in which point-group operations become local. We identify space-group codes whose code parameters exceed the reported same-blocklength, same-check-weight BB benchmarks. In five parameter-matched neutral-atom comparisons, reflection codes reduce the optimized movement cost in every case, by up to $60\%$, while folded placements also enable lower-overhead multilayer superconducting layouts. Treating spatial operations as a code-design variable therefore opens a route to topological codes jointly optimized for information protection and hardware geometry.

quant-ph

Fermion-to-Fermion Low-Density Parity-Check Codes

Simulating fermionic systems on qubit-based quantum computers often demands significant computational resources due to the requirement to map fermions to qubits. Thus, designing a fault-tolerant quantum computer that operates directly with fermions offers an effective solution to this challenge. Here, we introduce a protocol for fault-tolerant fermionic quantum computation utilizing fermion-to-fermion low-density parity-check (LDPC) codes. Our method employs a fermionic LDPC memory, which transfers its state to fermionic color code processors, where logical operations are subsequently performed. We propose using odd-weight logical Majorana operators to form the code space, serving as memory for the fermionic LDPC code, and provide an algorithm to identify these logical operators. We present examples showing that the encoding rate of fermionic codes often matches that of qubit codes, while the logical failure rate can be significantly lower than the physical error rate. Furthermore, we propose two methods for performing fermionic lattice surgery to facilitate state transfer. Finally, we simulate the dynamics of a fermionic system using our protocol, illustrating effective error suppression.

quant-ph

Self-dual Stacked Quantum Low-Density Parity-Check Codes

Quantum low-density parity-check (qLDPC) codes are promising candidates for fault-tolerant quantum computation due to their high encoding rates and distances. However, implementing logical operations using qLDPC codes presents significant challenges. Previous research has demonstrated that self-dual qLDPC codes facilitate the implementation of transversal Clifford gates. Here we introduce a method for constructing self-dual qLDPC codes by stacking non-self-dual qLDPC codes. Leveraging this methodology, we develop double-chain bicycle codes, double-layer bivariate bicycle (BB) codes, double-layer twisted BB codes, and double-layer reflection codes, many of which exhibit favorable code parameters. Additionally, we conduct numerical calculations to assess the performance of these codes as quantum memory under the circuit-level noise model, revealing that the logical failure rate can be significantly reduced with high pseudo-thresholds.

quant-ph