arXiv subjects

Christoph Kutter

Publications and source records attributed to Christoph Kutter.

4 recordsLinked to original sources

arXiv2026

Optimizing CMOS-compatible, superconducting titanium nitride resonators: Deposition conditions and structuring processes

We report on the fabrication and characterization of superconducting coplanar waveguide (CPW) resonators based on titanium nitride (TiN) thin films deposited on 200\,mm diameter high-resistivity Si(100) substrates. We systematically investigate how deposition conditions, dry-etch power and in-situ resist strip temperature affect morphology, superconducting properties and dielectric losses. By tuning reactive sputtering conditions, three distinct preferred out-of-plane crystal orientations - (111), (200), and a mix of both are achieved. Our results demonstrate that all films exhibit similar minimal two-level system (TLS) losses, with TiN111 exhibiting the lowest median TLS losses $\tilde{\delta}_\mathrm{TLS}$, and greater robustness against reoxidation. The applied structuring process, in contrast, has a far greater influence on the TLS loss than the crystal orientation of the TiN film and, consequently, the intrinsic material properties of the superconducting layer. The lowest TLS losses for all TiN depositions were achieved with a low power etch and low temperature resist strip. An additional buffered oxide etch (BOE) treatment could remove high-loss interfacial oxides at the metal-air (MA) and substrate-air (SA) interface and recover the etch-induced TLS losses. Consequently, TiN resonators exhibiting $\tilde{\delta}_\mathrm{TLS}$ values as low as $9.67 \times 10^{-7}$ were realized. The corresponding median low-power loss, $\tilde{\delta}_\mathrm{LP}$, amounts to $11.04 \times 10^{-7}$, which translates to an internal quality factor approaching one million. These findings highlight the critical role of process induced oxide formation at the MA and SA interfaces in limiting the performance of TiN resonators and provide a scalable, low-loss process compatible with industry-grade 200\,mm CMOS qubit fabrication workflows.

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arXiv2026

Surface Optimization of Superconducting Aluminum Resonators for Robust Quantum Device Fabrication

Aluminum (Al) remains the central material for superconducting qubits, and considerable effort has been devoted to optimizing its deposition and patterning for quantum devices. However, post-processing strategies focused on oxide removal of niobium (Nb) and tantalum (Ta) -based resonators using buffered oxide etch (BOE), which can not be used for Al. This challenge becomes particularly relevant for industry-scale fabrication with multi-chip bonding, where delays between sample preparation and cooldown require surface treatments that preserve low dielectric loss during extended exposure to ambient conditions. In this work, we investigate surface modification approaches for Al resonators subjected to a 24-hour delay prior to cryogenic measurement. Passivation using self-limiting oxygen and fluorine chemistries was evaluated utilizing different plasma processes. Remote oxygen plasma treatment reduced dielectric losses, in contrast to direct oxygen plasma. A fluorine-based plasma process was developed that passivated the Al surface for subsequent BOE treatment. However, the fluorine content in the surface resulted in higher loss, identifying fluorine as an unsuitable passivation material for Al resonators. Above all, selective oxide removal using HF (hydrogen fluoride) vapor and phosphoric acid yielded median dielectric losses as low as $\tilde{\delta}_\mathrm{LP} = 5.7 \times 10^{-7}$ ($Q_\mathrm{LP} \approx 1.7\,\mathrm{M}$) with $\tilde{\delta}_\mathrm{TLS} = 3.6 \times 10^{-7}$ ($Q_\mathrm{TLS} \approx 2.8\,\mathrm{M}$) in the single photon regime. Selective oxide removal provides a promising pathway for robust Al-based qubit fabrication, as it preserves low dielectric losses for a 24-hour delay before cooldown.

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arXiv2025

Stability studies on subtractively-fabricated CMOS-compatible superconducting transmon qubits

Developing fault-tolerant quantum processors with error correction demands large arrays of physical qubits whose key performance metrics (coherence times, control fidelities) must remain within specifications over both short and long timescales. Here we investigated the temporal stability of subtractively fabricated CMOS-compatible superconducting transmon qubits. During a single cooldown and over a period of 95 hours, we monitored several parameters for 8 qubits, including coherence times $T_1$ and $T_2^*$, which exhibit fluctuations originating primarily from the interaction between two-level system (TLS) defects and the host qubit. We also demonstrate that subtractively-fabricated superconducting quantum devices align with the theoretical predictions that higher mean lifetimes $T_1$ correspond to larger fluctuations. To assess long-term stability, we tracked two representative qubits over 10 cooldown cycles spanning more than one year. We observed an average total downward shift in both qubit transition frequencies of approximately 61 MHz within the thermal cycles considered. In contrast, readout resonator frequencies decreased only marginally. Meanwhile, $T_1$ exhibits fluctuations from cycle to cycle, but maintains a stable baseline value.

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arXiv2025

Wafer-Scale Characterization of Al/AlxOy/Al Josephson Junctions at Room Temperature

Josephson junctions (JJs) are the key element of many devices operating at cryogenic temperatures. Development of time-efficient wafer-scale JJ characterization for process optimization and control of JJ fabrication is essential. Such statistical characterization has to rely on room temperature techniques since cryogenic measurements typically used for JJs are too time consuming and unsuitable for wafer-scale characterization. In this work, we show that from room temperature capacitance and current-voltage measurements, with proper data analysis, we can independently obtain useful parameters of the JJs on wafer-scale, like oxide thickness, tunnel coefficient, and interfacial defect densities. Moreover, based on detailed analysis of current vs voltage characteristics, different charge transport mechanisms across the junctions can be distinguished. We exemplary demonstrate the worth of these methods by studying junctions fabricated on 200 mm wafers with an industrially scale-able concept based on subtractive processing using only CMOS compatible tools. From these studies, we find that our subtractive fabrication approach yields junctions with quite homogeneous average oxide thickness across the full wafers, with a spread of less then 3$\,$%. The analysis also revealed a variation of the tunnel coefficient with oxide thickness, pointing to a stoichiometry gradient across the junctions' oxide width. Moreover, we estimated relatively low interfacial defect densities in the range of 70 - 5000$\,$defects/cm$^2$ for our junctions and established that the density increased with decreasing oxide thickness, indicating that the wet etching process applied in the JJs fabrication for oxide thickness control leads to formation of interfacial trap state

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