arXiv subjects

Christopher C. Escott

Publications and source records attributed to Christopher C. Escott.

At least 19 recordsLinked to original sources

arXiv2026

Optimal operating temperature for industry-compatible silicon spin quantum computing: colder is not necessarily better

Silicon spin qubits are a leading candidate for large-scale quantum computing owing to their compatibility with semiconductor manufacturing. However, scaling to useful fault-tolerant processors will likely generate thermal loads that exceed the cooling power available at millikelvin temperatures. Raising the operating temperature eases cooling requirements but reduces gate fidelity, increasing the overhead of quantum error correction. Identifying the operating temperature that minimizes total power consumption is therefore a key challenge for commercially viable quantum computers. Here, we use gate set tomography to benchmark two-qubit silicon chips fabricated in both industrial and academic environments over a range of temperatures. Elevated temperatures substantially shorten coherence times and increase gate and state-preparation-and-measurement infidelities. Based on these measurements, we develop a general power model for silicon quantum computers that combines cryogenic cooling requirements with error-correction overheads. We show that a finite optimal operating temperature exists and is strongly influenced by a crossover temperature near 1 K in current devices, above which gate fidelity degrades rapidly. These results connect device-level fidelity limitations to system-level power requirements, providing design guidelines for large-scale silicon quantum computers.

quant-ph↗

arXiv2026

Gate Stack Engineering for High-Mobility and Low-Noise SiMOS Quantum Devices

We systematically investigate the interplay between materials engineering, quantum transport, and low-frequency charge noise in silicon metal--oxide--semiconductor (SiMOS) quantum devices. By combining Hall-bar transport measurements with charge-noise spectroscopy of gate-defined quantum dots, we identify correlations between gate-stack design, carrier mobility, and electrostatic noise, providing an experimental case study of material and process dependencies relevant to low-noise, high-mobility operation. Hall-bar studies reveal that increasing the atomic-layer-deposition temperature of Al$_2$O$_3$ markedly enhances mobility, whereas the choice of oxidant has little impact. Devices incorporating HfO$_2$ exhibit improved carrier mobility, an interesting observation that can plausibly be attributed to defect passivation associated with aluminum diffusion from the gate metal into the HfO$_2$ layer. Charge-noise measurements show a strong correlation between higher mobility and reduced noise, with TiPd-gated devices displaying both degraded transport and elevated charge noise. In contrast, the poly-Si-gated CMOS-foundry device achieves the lowest noise levels. Finally, dual-feedback dot--sensor stability mapping demonstrates enhanced charge stability in devices with the gate stacks studied here, underscoring their promise for scalable, high-fidelity silicon spin-qubit platforms.

cond-mat.mes-hall↗

arXiv2025

Eight-Qubit Operation of a 300 mm SiMOS Foundry-Fabricated Device

Silicon spin qubits are a promising platform for quantum computing due to their high coherence, controllability, and CMOS manufacturability, yet scalable implementations have so far been limited to a few qubits. Here, to take a step towards larger qubit systems, we tune and coherently control an eight-dot linear array of silicon spin qubits fabricated in a 300~mm CMOS-compatible foundry process, establishing operational scalability beyond the two-qubit regime. All eight qubits are successfully tuned and characterized as four double-dot pairs, exhibiting Ramsey dephasing times $T_2^*$ up to 41(2)$~\mu$s and Hahn-echo coherence times $T_2^{\mathrm{Hahn}}$ up to 1.31(4)$~$ms. Readout of the central four qubits is achieved via a cascaded charge-sensing protocol, enabling high-fidelity measurements of the entire multi-qubit array in a two step process. Additionally, we demonstrate a two-qubit gate operation between adjacent qubits with low phase noise. We show that silicon spin qubit arrays can be scaled to medium-sized arrays of 8 qubits while maintaining system coherence.

quant-ph↗

arXiv2025

Coupling a $^{73}$Ge nuclear spin to an electrostatically defined quantum dot

Single nuclear spins in silicon are a promising resource for quantum technologies due to their long coherence times and excellent control fidelities. Qubits and qudits have been encoded on donor nuclei, with successful demonstrations of Bell states and quantum memories on the spin-1/2 $^{31}$P and cat-qubits on the spin-7/2 $^{123}$Sb nuclei. Isoelectronic nuclear spins coupled to gate-defined quantum dots, such as the naturally occurring $^{29}$Si isotope, possess no additional charge and allow for the coupled electron to be shuttled without destroying the nuclear spin coherence. Here, we demonstrate the coupling and readout of a spin-9/2 $^{73}$Ge nuclear spin to a gate-defined quantum dot in SiMOS. The $^{73}$Ge nucleus was implanted by isotope-selective ion-implantation. We observe the hyperfine interaction (HFI) to the coupled quantum dot electron and are able to tune it from 180 kHz to 350 kHz, through the voltages applied to the lateral gate electrodes. This work lays the foundation for future spin control experiments on the spin-9/2 qudit as well as more advanced experiments such as entanglement distribution between distant nuclear spins or repeated weak measurements.

cond-mat.mes-hall↗

arXiv2025

Scalable quantum current source on commercial CMOS process technology

Many quantum technologies require a precise electrical current standard that can only be achieved with expensive cryogenics, or through the secondary standards, such as resistance or voltage. Silicon-based charge pumps could provide such a standard in an inherently scalable way, through their compatibility with complementary metal-oxide-semiconductor (CMOS) fabrication methods. However, coherent quantized charge transfer has so far been demonstrated only in nanoscale devices that are custom-fabricated in academic cleanrooms or research technology foundries. Here, we show that a CMOS device manufactured with commercial 22-nm process node can be used to define a quantum current standard in the International System of Units (SI). We measure an accuracy of (1.2 +/- 0.1)E-3 A/A at 50 MHz with reference to SI voltage and resistance standards in a pumped helium system. We then propose a practical monolithic CMOS chip that incorporates one million parallel connected charge pumps along with on-chip control electronics. This chip could be operated as a table-top primary standard that can be easily integrated with CMOS electronics, generating quantum currents of up to microampere levels.

physics.app-ph↗

arXiv2025

Enhancement of Electric Drive in Silicon Quantum Dots with Electric Quadrupole Spin Resonance

Quantum computation with electron spin qubits requires coherent and efficient manipulation of these spins, typically accomplished through the application of alternating magnetic or electric fields for electron spin resonance (ESR). In particular, electrical driving allows us to apply localized fields on the electrons, which benefits scale-up architectures. However, we have found that Electric Dipole Spin Resonance (EDSR) is insufficient for modeling the Rabi behavior in recent experimental studies. Therefore, we propose that the electron spin is being driven by a new method of electric spin qubit control which generalizes the spin dynamics by taking into account a quadrupolar contribution of the quantum dot: electric quadrupole spin resonance (EQSR). In this work, we explore the electric quadrupole driving of a quantum dot in silicon, specifically examining the cases of 5 and 13 electron occupancies.

cond-mat.mes-hall↗

arXiv2024

A 2x2 quantum dot array in silicon with fully tuneable pairwise interdot coupling

Recent advances in semiconductor spin qubits have achieved linear arrays exceeding ten qubits. Moving to two-dimensional (2D) qubit arrays is a critical next step to advance towards fault-tolerant implementations, but it poses substantial fabrication challenges, particularly because enabling control of nearest-neighbor entanglement requires the incorporation of interstitial exchange gates between quantum dots in the qubit architecture. In this work, we present a 2D array of silicon metal-oxide-semiconductor (MOS) quantum dots with tunable interdot coupling between all adjacent dots. The device is characterized at 4.2 K, where we demonstrate the formation and isolation of double-dot and triple-dot configurations. We show control of all nearest-neighbor tunnel couplings spanning up to 30 decades per volt through the interstitial exchange gates and use advanced modeling tools to estimate the exchange interactions that could be realized among qubits in this architecture. These results represent a significant step towards the development of 2D MOS quantum processors compatible with foundry manufacturing techniques.

cond-mat.mes-hall↗

arXiv2024

A 300 mm foundry silicon spin qubit unit cell exceeding 99% fidelity in all operations

Fabrication of quantum processors in advanced 300 mm wafer-scale complementary metal-oxide-semiconductor (CMOS) foundries provides a unique scaling pathway towards commercially viable quantum computing with potentially millions of qubits on a single chip. Here, we show precise qubit operation of a silicon two-qubit device made in a 300 mm semiconductor processing line. The key metrics including single- and two-qubit control fidelities exceed 99% and state preparation and measurement fidelity exceeds 99.9%, as evidenced by gate set tomography (GST). We report coherence and lifetimes up to $T_\mathrm{2}^{\mathrm{*}} = 30.4$ $\mu$s, $T_\mathrm{2}^{\mathrm{Hahn}} = 803$ $\mu$s, and $T_1 = 6.3$ s. Crucially, the dominant operational errors originate from residual nuclear spin carrying isotopes, solvable with further isotopic purification, rather than charge noise arising from the dielectric environment. Our results answer the longstanding question whether the favourable properties including high-fidelity operation and long coherence times can be preserved when transitioning from a tailored academic to an industrial semiconductor fabrication technology.

cond-mat.mes-hall↗

arXiv2024

CMOS compatibility of semiconductor spin qubits

Several domains of society will be disrupted once millions of high-quality qubits can be brought together to perform fault-tolerant quantum computing (FTQC). All quantum computing hardware available today is many orders of magnitude removed from the requirements for FTQC. The intimidating challenges associated with integrating such complex systems have already been addressed by the semiconductor industry -hence many qubit makers have retrofitted their technology to be CMOS-compatible. This compatibility, however, can have varying degrees ranging from the mere ability to fabricate qubits using a silicon wafer as a substrate, all the way to the co-integration of qubits with high-yield, low-power advanced electronics to control these qubits. Extrapolating the evolution of quantum processors to future systems, semiconductor spin qubits have unique advantages in this respect, making them one of the most serious contenders for large-scale FTQC. In this review, we focus on the overlap between state-of-the-art semiconductor spin qubit systems and CMOS industry Very Large-Scale Integration (VLSI) principles. We identify the main differences in spin qubit operation, material, and system requirements compared to well-established CMOS industry practices. As key players in the field are looking to collaborate with CMOS industry partners, this review serves to accelerate R&D towards the industrial scale production of FTQC processors.

cond-mat.mes-hall↗

arXiv2024

Violating Bell's inequality in gate-defined quantum dots

Superior computational power promised by quantum computers utilises the fundamental quantum mechanical principle of entanglement. However, achieving entanglement and verifying that the generated state does not follow the principle of local causality has proven difficult for spin qubits in gate-defined quantum dots, as it requires simultaneously high concurrence values and readout fidelities to break the classical bound imposed by Bell's inequality. Here we employ heralded initialization and calibration via gate set tomography (GST), to reduce all relevant errors and push the fidelities of the full 2-qubit gate set above 99 %, including state preparation and measurement (SPAM). We demonstrate a 97.17 % Bell state fidelity without correcting for readout errors and violate Bell's inequality with a Bell signal of S = 2.731 close to the theoretical maximum of $2\sqrt{2}$. Our measurements exceed the classical limit even at elevated temperatures of 1.1 K or entanglement lifetimes of 100 $\mu s$.

cond-mat.mes-hall↗

arXiv2024

Spin Qubits with Scalable milli-kelvin CMOS Control

A key virtue of spin qubits is their sub-micron footprint, enabling a single silicon chip to host the millions of qubits required to execute useful quantum algorithms with error correction. With each physical qubit needing multiple control lines however, a fundamental barrier to scale is the extreme density of connections that bridge quantum devices to their external control and readout hardware. A promising solution is to co-locate the control system proximal to the qubit platform at milli-kelvin temperatures, wired-up via miniaturized interconnects. Even so, heat and crosstalk from closely integrated control have potential to degrade qubit performance, particularly for two-qubit entangling gates based on exchange coupling that are sensitive to electrical noise. Here, we benchmark silicon MOS-style electron spin qubits controlled via heterogeneously-integrated cryo-CMOS circuits with a low enough power density to enable scale-up. Demonstrating that cryo-CMOS can efficiently enable universal logic operations for spin qubits, we go on to show that mill-kelvin control has little impact on the performance of single- and two-qubit gates. Given the complexity of our milli-kelvin CMOS platform, with some 100-thousand transistors, these results open the prospect of scalable control based on the tight packaging of spin qubits with a chiplet style control architecture.

quant-ph↗

arXiv2023

Impact of electrostatic crosstalk on spin qubits in dense CMOS quantum dot arrays

Quantum processors based on integrated nanoscale silicon spin qubits are a promising platform for highly scalable quantum computation. Current CMOS spin qubit processors consist of dense gate arrays to define the quantum dots, making them susceptible to crosstalk from capacitive coupling between a dot and its neighbouring gates. Small but sizeable spin-orbit interactions can transfer this electrostatic crosstalk to the spin g-factors, creating a dependence of the Larmor frequency on the electric field created by gate electrodes positioned even tens of nanometers apart. By studying the Stark shift from tens of spin qubits measured in nine different CMOS devices, we developed a theoretical frawework that explains how electric fields couple to the spin of the electrons in increasingly complex arrays, including those electric fluctuations that limit qubit dephasing times $T_2^*$. The results will aid in the design of robust strategies to scale CMOS quantum technology.

cond-mat.mes-hall↗

arXiv2023

High-fidelity operation and algorithmic initialisation of spin qubits above one kelvin

The encoding of qubits in semiconductor spin carriers has been recognised as a promising approach to a commercial quantum computer that can be lithographically produced and integrated at scale. However, the operation of the large number of qubits required for advantageous quantum applications will produce a thermal load exceeding the available cooling power of cryostats at millikelvin temperatures. As the scale-up accelerates, it becomes imperative to establish fault-tolerant operation above 1 kelvin, where the cooling power is orders of magnitude higher. Here, we tune up and operate spin qubits in silicon above 1 kelvin, with fidelities in the range required for fault-tolerant operation at such temperatures. We design an algorithmic initialisation protocol to prepare a pure two-qubit state even when the thermal energy is substantially above the qubit energies, and incorporate radio-frequency readout to achieve fidelities up to 99.34 per cent for both readout and initialisation. Importantly, we demonstrate a single-qubit Clifford gate fidelity of 99.85 per cent, and a two-qubit gate fidelity of 98.92 per cent. These advances overcome the fundamental limitation that the thermal energy must be well below the qubit energies for high-fidelity operation to be possible, surmounting a major obstacle in the pathway to scalable and fault-tolerant quantum computation.

quant-ph↗

arXiv2023

Improved Single-Shot Qubit Readout Using Twin RF-SET Charge Correlations

High fidelity qubit readout is critical in order to obtain the thresholds needed to implement quantum error correction protocols and achieve fault-tolerant quantum computing. Large-scale silicon qubit devices will have densely-packed arrays of quantum dots with multiple charge sensors that are, on average, farther away from the quantum dots, entailing a reduction in readout fidelities. Here, we present a readout technique that enhances the readout fidelity in a linear SiMOS 4-dot array by amplifying correlations between a pair of single-electron transistors, known as a twin SET. By recording and subsequently correlating the twin SET traces as we modulate the dot detuning across a charge transition, we demonstrate a reduction in the charge readout infidelity by over one order of magnitude compared to traditional readout methods. We also study the spin-to-charge conversion errors introduced by the modulation technique, and conclude that faster modulation frequencies avoid relaxation-induced errors without introducing significant spin flip errors, favouring the use of the technique at short integration times. This method not only allows for faster and higher fidelity qubit measurements, but it also enhances the signal corresponding to charge transitions that take place farther away from the sensors, enabling a way to circumvent the reduction in readout fidelities in large arrays of qubits.

cond-mat.mes-hall↗

arXiv2023

Path integral simulation of exchange interactions in CMOS spin qubits

The boom of semiconductor quantum computing platforms created a demand for computer-aided design and fabrication of quantum devices. Path integral Monte Carlo (PIMC) can have an important role in this effort because it intrinsically integrates strong quantum correlations that often appear in these multi-electron systems. In this paper we present a PIMC algorithm that estimates exchange interactions of three-dimensional electrically defined quantum dots. We apply this model to silicon metal-oxide-semiconductor (MOS) devices and we benchmark our method against well-tested full configuration interaction (FCI) simulations. As an application, we study the impact of a single charge trap on two exchanging dots, opening the possibility of using this code to test the tolerance to disorder of CMOS devices. This algorithm provides an accurate description of this system, setting up an initial step to integrate PIMC algorithms into development of semiconductor quantum computers.

cond-mat.mes-hall↗

arXiv2023

Bounds to electron spin qubit variability for scalable CMOS architectures

Spins of electrons in CMOS quantum dots combine exquisite quantum properties and scalable fabrication. In the age of quantum technology, however, the metrics that crowned Si/SiO2 as the microelectronics standard need to be reassessed with respect to their impact upon qubit performance. We chart the spin qubit variability due to the unavoidable atomic-scale roughness of the Si/SiO$_2$ interface, compiling experiments in 12 devices, and developing theoretical tools to analyse these results. Atomistic tight binding and path integral Monte Carlo methods are adapted for describing fluctuations in devices with millions of atoms by directly analysing their wavefunctions and electron paths instead of their energy spectra. We correlate the effect of roughness with the variability in qubit position, deformation, valley splitting, valley phase, spin-orbit coupling and exchange coupling. These variabilities are found to be bounded and lie within the tolerances for scalable architectures for quantum computing as long as robust control methods are incorporated.

quant-ph↗

arXiv2023

Assessment of error variation in high-fidelity two-qubit gates in silicon

Achieving high-fidelity entangling operations between qubits consistently is essential for the performance of multi-qubit systems and is a crucial factor in achieving fault-tolerant quantum processors. Solid-state platforms are particularly exposed to errors due to materials-induced variability between qubits, which leads to performance inconsistencies. Here we study the errors in a spin qubit processor, tying them to their physical origins. We leverage this knowledge to demonstrate consistent and repeatable operation with above 99% fidelity of two-qubit gates in the technologically important silicon metal-oxide-semiconductor (SiMOS) quantum dot platform. We undertake a detailed study of these operations by analysing the physical errors and fidelities in multiple devices through numerous trials and extended periods to ensure that we capture the variation and the most common error types. Physical error sources include the slow nuclear and electrical noise on single qubits and contextual noise. The identification of the noise sources can be used to maintain performance within tolerance as well as inform future device fabrication. Furthermore, we investigate the impact of qubit design, feedback systems, and robust gates on implementing scalable, high-fidelity control strategies. These results are achieved by using three different characterization methods, we measure entangling gate fidelities ranging from 96.8% to 99.8%. Our analysis tools identify the causes of qubit degradation and offer ways understand their physical mechanisms. These results highlight both the capabilities and challenges for the scaling up of silicon spin-based qubits into full-scale quantum processors.

quant-ph↗

arXiv2022

Jellybean quantum dots in silicon for qubit coupling and on-chip quantum chemistry

The small size and excellent integrability of silicon metal-oxide-semiconductor (SiMOS) quantum dot spin qubits make them an attractive system for mass-manufacturable, scaled-up quantum processors. Furthermore, classical control electronics can be integrated on-chip, in-between the qubits, if an architecture with sparse arrays of qubits is chosen. In such an architecture qubits are either transported across the chip via shuttling, or coupled via mediating quantum systems over short-to-intermediate distances. This paper investigates the charge and spin characteristics of an elongated quantum dot -- a so-called jellybean quantum dot -- for the prospects of acting as a qubit-qubit coupler. Charge transport, charge sensing and magneto-spectroscopy measurements are performed on a SiMOS quantum dot device at mK temperature, and compared to Hartree-Fock multi-electron simulations. At low electron occupancies where disorder effects and strong electron-electron interaction dominate over the electrostatic confinement potential, the data reveals the formation of three coupled dots, akin to a tunable, artificial molecule. One dot is formed centrally under the gate and two are formed at the edges. At high electron occupancies, these dots merge into one large dot with well-defined spin states, verifying that jellybean dots have the potential to be used as qubit couplers in future quantum computing architectures.

cond-mat.mes-hall↗