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Christopher Day

Publications and source records attributed to Christopher Day.

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Towards Heterogeneous Exascale CFD with a Single Fortran Code Base: OpenMP Target Acceleration of the High-Order Unstructured Solver UCNS3D

Heterogeneous exascale systems are reshaping computational fluid dynamics, yet rewriting mature high-order solvers for accelerators can fragment code bases and weaken reproducibility. We present a single-source OpenMP target modernisation of UCNS3D, a high-order unstructured finite-volume solver for compressible flows. The common CPU/GPU implementation preserves its numerical formulation, Fortran code base, and workflows. Rather than porting isolated kernels, we enable the complete explicit time-advancement path: high-order reconstruction, gradient evaluation, inviscid and viscous fluxes, boundary treatment, halo exchange, and solution update. The implementation uses persistent target data regions, flat run-time arrays, compile-time sizing of temporary storage, explicit local algebra, target-callable routines, and GPU-aware MPI with device-resident buffers. These choices address the irregular stencils, complex data structures, and substantial temporary storage of high-order unstructured CFD. Verification using the compressible Taylor-Green vortex shows CPU and GPU dissipation histories agreeing to machine precision on LUMI and with published reference data. A single-node run on the ARCHER2 GPU platform provides an independent portability check. End-to-end performance is evaluated on fully populated nodes using Taylor-Green vortex, LM1021 sonic-boom, and NASA high-lift CRM benchmarks. Relative to the previous production implementation, the refactored CPU path is 1.27-1.67 times faster, while GPU offload delivers same-node speed-ups of 2.71-4.05 and 84-101 percent strong-scaling efficiency. The results show that standards-based OpenMP provides portable, production-scale acceleration without sacrificing numerical fidelity, CPU performance, or software sustainability.

math-ph

Investigations of multi-socket high core count RISC-V for HPC workloads

Whilst RISC-V has become popular in fields such as embedded computing, it is yet to find mainstream success in High Performance Computing (HPC). However, the 64-core RISC-V Sophon SG2042 is a potential game changer as it provides a commodity available CPU with much higher core count than existing technologies. In this work we benchmark the SG2042 CPU hosted in an experimental, dual-socket, system to explore the performance properties of the CPU when running a common HPC benchmark suite across sockets. Earlier benchmarks found that, on the Milk-V Pioneer workstation, whilst the SG2042 performs well for compute bound codes, it struggles when pressure is placed on the memory subsystem. The performance results reported here confirm that, even on a different system, these memory performance limitations are still present and hence inherent in the CPU. However, a multi-socket configuration does enable the CPU to scale to a larger number of threads which, in the main, delivers an improvement in performance and-so this is a realistic system configuration for the HPC community.

cs.DC