arXiv subjects

Chuan Zhang

Publications and source records attributed to Chuan Zhang.

75 records · Page 5Linked to original sources

arXiv2011

Reduced-Latency SC Polar Decoder Architectures

Polar codes have become one of the most favorable capacity achieving error correction codes (ECC) along with their simple encoding method. However, among the very few prior successive cancellation (SC) polar decoder designs, the required long code length makes the decoding latency high. In this paper, conventional decoding algorithm is transformed with look-ahead techniques. This reduces the decoding latency by 50%. With pipelining and parallel processing schemes, a parallel SC polar decoder is proposed. Sub-structure sharing approach is employed to design the merged processing element (PE). Moreover, inspired by the real FFT architecture, this paper presents a novel input generating circuit (ICG) block that can generate additional input signals for merged PEs on-the-fly. Gate-level analysis has demonstrated that the proposed design shows advantages of 50% decoding latency and twice throughput over the conventional one with similar hardware cost.

cs.AR↗

arXiv2011

Low-Latency SC Decoder Architectures for Polar Codes

Nowadays polar codes are becoming one of the most favorable capacity achieving error correction codes for their low encoding and decoding complexity. However, due to the large code length required by practical applications, the few existing successive cancellation (SC) decoder implementations still suffer from not only the high hardware cost but also the long decoding latency. This paper presents novel several approaches to design low-latency decoders for polar codes based on look-ahead techniques. Look-ahead techniques can be employed to reschedule the decoding process of polar decoder in numerous approaches. However, among those approaches, only well-arranged ones can achieve good performance in terms of both latency and hardware complexity. By revealing the recurrence property of SC decoding chart, the authors succeed in reducing the decoding latency by 50% with look-ahead techniques. With the help of VLSI-DSP design techniques such as pipelining, folding, unfolding, and parallel processing, methodologies for four different polar decoder architectures have been proposed to meet various application demands. Sub-structure sharing scheme has been adopted to design the merged processing element (PE) for further hardware reduction. In addition, systematic methods for construction refined pipelining decoder (2nd design) and the input generating circuits (ICG) block have been given. Detailed gate-level analysis has demonstrated that the proposed designs show latency advantages over conventional ones with similar hardware cost.

cs.AR↗

arXiv2002

Status Report of the Inter-Laboratory Task Force on Remote Operation

In February 2000, the International Committee for Future Accelerators initiated a study of a new model for international collaboration on a future large accelerator project, the Global Accelerator Network. The study is based on a model of a facility, which is remote from most of the collaborating institutions. It is designed, built and operated by a collaboration of equal partner institutions distributed around the world. According to this model, the expert-staff from each laboratory remains based at their home institution but continues to participate in the operation of the machine after construction. This report summarizes the conclusions of the Task Force on Remote Operation, which investigated the general and technical implications of far-remote operations.

physics.acc-ph↗