Chun Kit Lam | Searcharxiv

arXiv2026

Series-Parallel-Loop Decompositions of Control-flow Graphs

Control-flow graphs (CFGs) of structured programs are well known to exhibit strong sparsity properties. Traditionally, this sparsity has been modeled using graph parameters such as treewidth and pathwidth, enabling the development of faster parameterized algorithms for tasks in compiler optimization, model checking, and program analysis. However, these parameters only approximate the structural constraints of CFGs: although every structured CFG has treewidth at most~7, many graphs with treewidth at most~7 cannot arise as CFGs. As a result, existing parameterized techniques are optimized for a substantially broader class of graphs than those encountered in practice. In this work, we introduce a new grammar-based decomposition framework that characterizes \emph{exactly} the class of control-flow graphs generated by structured programs. Our decomposition is intuitive, mirrors the syntactic structure of programs, and remains fully compatible with the dynamic-programming paradigm of treewidth-based methods. Using this framework, we design improved algorithms for two classical compiler optimization problems: \emph{Register Allocation} and \emph{Lifetime-Optimal Speculative Partial Redundancy Elimination (LOSPRE)}. Extensive experimental evaluation demonstrates significant performance improvements over previous state-of-the-art approaches, highlighting the benefits of using decompositions tailored specifically to CFGs.

cs.PL↗

arXiv2021

Combining processing throughput, low latency and timing accuracy in experiment control

We ported the firmware of the ARTIQ experiment control infrastructure to an embedded system based on a commercial Xilinx Zynq-7000 system-on-chip. It contains high-performance hardwired CPU cores integrated with FPGA fabric. As with previous ARTIQ systems, the FPGA fabric is responsible for timing all I/O signals to and from peripherals, thereby retaining the exquisite precision required by most quantum physics experiments. A significant amount of latency is incurred by the hardwired interface between the CPU core and FPGA fabric of the Zynq-7000 chip; creative use of the CPU's cache-coherent accelerator ports and the CPU's event flag allowed us to reduce this latency and achieve better I/O performance than previous ARTIQ systems. The performance of the hardwired CPU core, in particular when floating-point computation is involved, greatly exceeds that of previous ARTIQ systems based on a softcore CPU. This makes it interesting to execute intensive computations on the embedded system, with a low-latency path to the experiment. We extended the ARTIQ compiler so that many mathematical functions and matrix operations can be programmed by the user, using the familiar NumPy syntax.

physics.ins-det↗