arXiv subjects

Claus Kestel

Publications and source records attributed to Claus Kestel.

5 recordsLinked to original sources

arXiv2026

Towards a Unified Coding Scheme for 6G

The growing demand for higher data rates necessitates continuous innovations in wireless communication systems, particularly with the emergence of 6G. Channel coding plays a crucial role in this evolution. In 5G systems, rate-adaptive raptor-like quasi-cyclic irregular low-density parity-check codes are used for the data link, while polar codes with successive cancellation list decoding handle short messages on the synchronization channel. However, to meet the stringent requirements of future 6G systems, a versatile and unified coding scheme should be developed - one that offers competitive error-correcting performance alongside low complexity encoding and decoding schemes that enable energy-efficient hardware implementations. This white paper outlines the vision for such a unified coding scheme. We explore various 6G communication scenarios that pose new challenges to channel coding and provide a first analysis of potential solutions.

cs.IT↗

arXiv2024

High Throughput Polar Code Decoders with Information Bottleneck Quantization

In digital baseband processing, the forward error correction (FEC) unit belongs to the most demanding components in terms of computational complexity and power consumption. Hence, efficient implementation of FEC decoders is crucial for next generation mobile broadband standards and an ongoing research topic. Quantization has a significant impact on the decoder area, power consumption and throughput. Thus, lower bit-widths are preferred for efficient implementations but degrade the error-correction capability. To address this issue, a non-uniform quantization based on the Information Bottleneck (IB) method was proposed that enables a low bit width while maintaining the essential information. Many investigations on the use of IB method for Low-density parity-check code (LDPC) decoders exist and have shown its advantages from an implementation perspective. However, for polar code decoder implementations, there exists only one publication that is not based on the state-of-the-art Fast-SSC decoding algorithm, and only synthesis implementation results without energy estimation are shown. In contrast, our paper presents several optimized Fast Simplified Successive-Cancellation (Fast-SSC) polar code decoder implementations using IB-based quantization with placement&routing results in an advanced 12 nm FinFET technology. Gains of up to 16% in area and 13% in energy efficiency are achieved with IB-based quantization at a Frame Error Rate (FER) of 10-7 and a Polar Code of N = 1024, R = 0.5 compared to state-of-the-art decoders.

cs.IT↗

arXiv2023

Row-Merged Polar Codes: Analysis, Design and Decoder Implementation

Row-merged polar codes are a family of pre-transformed polar codes (PTPCs) with little precoding overhead. Providing an improved distance spectrum over plain polar codes, they are capable to perform close to the finite-length capacity bounds. However, there is still a lack of efficient design procedures for row-merged polar codes. Using novel weight enumeration algorithms with low computational complexity, we propose a design methodology for row-merged polar codes that directly considers their minimum distance properties. The codes significantly outperform state-of-the-art cyclic redundancy check (CRC)-aided polar codes under successive cancellation list (SCL) decoding in error-correction performance. Furthermore, we present fast simplified successive cancellation list (Fast-SSCL) decoding of PTPCs, based on which we derive a high-throughput, unrolled architecture template for fully pipelined decoders. Implementation results of SCL decoders for row-merged polar codes in a 12 nm technology additionally demonstrate the superiority of these codes with respect to the implementation costs, compared to state-of-the-art reference decoder implementations.

cs.IT↗

arXiv2023

Successive Cancellation Automorphism List Decoding of Polar Codes

The discovery of suitable automorphisms of polar codes gained a lot of attention by applying them in Automorphism Ensemble Decoding (AED) to improve the error-correction performance, especially for short block lengths. This paper introduces Successive Cancellation Automorphism List (SCAL) decoding of polar codes as a novel application of automorphisms in advanced Successive Cancellation List (SCL) decoding. Initialized with L permutations sampled from the automorphism group, a superposition of different noise realizations and path splitting takes place inside the decoder. In this way, the SCAL decoder automatically adapts to the channel conditions and outperforms the error-correction performance of conventional SCL decoding and AED. For a polar code of length 128, SCAL performs near Maximum Likelihood (ML) decoding with L=8, in contrast to M=16 needed decoder cores in AED. Application-Specific Integrated Circuit (ASIC) implementations in a 12 nm technology show that high-throughput, pipelined SCAL decoders outperform AED in terms of energy efficiency and power density, and SCL decoders additionally in area efficiency.

cs.IT↗

arXiv2023

Automorphism Ensemble Polar Code Decoders for 6G URLLC

The URLLC scenario in the upcoming 6G standard requires low latency and ultra reliable transmission, i.e., error correction towards ML performance. Achieving near-ML performance is very challenging especially for short block lengths. Polar codes are a promising candidate and already part of the 5G standard. The Successive Cancellation List (SCL) decoding algorithm provides very good error correction performance but at the cost of high computational decoding complexity resulting in large latency and low area and energy efficiency. Recently, Automorphism Ensemble Decoding (AED) gained a lot of attention to improve the error correction capability. In contrast to SCL, AED performs several low-complexity (e.g., SC) decoding in parallel. However, it is an open question whether AED can compete with sophisticated SCL decoders, especially from an implementation perspective in state of the art silicon technologies. In this paper we present an elaborated AED architecture that uses an advanced path metric based candidate selection to reduce the implementation complexity and compare it to state of the art SCL decoders in a 12nm FinFET technology. Our AED implementation outperform state of the art SCL decoders by up to 4.4x in latency, 8.9x in area efficiency and 4.6x in energy efficiency, while providing the same or even better error correction performance.

cs.IT↗