Searcharxiv⌕ Search

arXiv subjects

Daniel Etiemble

Publications and source records attributed to Daniel Etiemble.

13 recordsLinked to original sources
arXiv2022

Ternary and Quaternary CNTFET Full Adders are less efficient than the Binary Ones for Carry-Propagate Adders

In Carry Propagate Adders, carry propagation is the critical delay. The most efficient scheme is to generate Cout0 (Cin=0) and Cout1(Cin=1) and multiplex the correct output according to Cin. For any radix, the carry output is always 0/1. We present two versions of ternary adders with Cin = (0V, Vdd/2) and Cin = (0V, Vdd) and two versions of quaternary adders with Cin = (0V, Vdd/3) and Cin = (0V, Vdd). Using full swing Vdd for Cin reduces the propagation delays for ternary and quaternary adders. 6-bit, 4-trit and 3-quit CPAs are then compared.

cs.AR↗
arXiv2022

Two New CNTFET Quaternary Full Adders for Carry-Propagate Adders

In Carry Propagate Adders, carry propagation is the critical delay. For the 1-digit adders that they use, the most efficient scheme is to generate two intermediate carries: C$_{out0}$ ($C_{in}$=0) and $C_{out1}$($C_{in}$=1). Then multiplex them to produce the correct output according to $C_{in}$. For any radix, the carry output has always a logical value 0 or 1. We show that using 0 and $V_{dd}$ levels for input and output carries instead of 0 and $V_{dd}$/3 in quaternary full adders significantly reduce the carry propagation. We compare such a quaternary full adder with binary full adders to implement N-digit carry propagate adders.

cs.AR↗
arXiv2022

Technologies and Computing Paradigms: Beyond Moore's law?

As it is pretty sure that Moore's law will end some day, questioning about the post-Moore era is more than interesting. Similarly, looking for new computing paradigms that could provide solutions is important. Revisiting the history of digital electronics since the 60's provide significant insights on the conditions for the success of a new emerging technology to replace the currently dominant one. Specifically, the past shows when constraints and « walls » have contribute to evolution through improved technical techniques and when they have provoked changes of technologies (evolution versus breakthrough). The main criteria for a new technology or a new computing paradigm is a significant performance improvement (at least one order of magnitude). Cost, space requirement, power and scalability are the other important parameters.

cs.ET↗
arXiv2022

CNTFET quaternary multipliers are less efficient than the corresponding binary ones

We compare N*N quaternary digit and 2N*2N bit CNTFET multipliers in terms of Worst case delay, Chip area, Power and Power Delay Product (PDP) for N=1, N=2 and N=4. Both multipliers use Wallace reduction trees. HSpice simulations with 32-nm CNTFET parameters shows that the binary implementations are always more efficient: the 1*1 quit multiplier is far more complex than a 1*1 bit multiplier (AND gate) and generate both product and a carry terms. Even with half number of terms, the quaternary reduction tree has the same number of terms than the binary one, and uses quaternary adders that are also more complicated than the binary ones. The quaternary multipliers have larger worst case delays, more power dissipation and far more chip areas than the binary ones computing the same amount of information.

cs.ET↗
arXiv2021

Best CNTFET Ternary Adders?

The MUX implementation of ternary half adders and full adders using predecessor and successor functions lead to the most efficient efficient implementation using the smallest transistor count. These designs are compared with the binary implementation of the corresponding half adders and full adders using the MUX technique or the typical complementary CMOS circuit style. The transistor count ratio between ternary and binary implementations is always greater than the information ratio ($log_2(3)/log_2(2)$ = 1.585) between ternary and binary wires.

cs.AR↗
arXiv2020

Multivalued circuits and Interconnect issues

Many papers have presented multi-valued circuits in various technologies as a solution to reduce or solve interconnection issues in binary circuits. This assumption is discussed. While 4-valued signaling could divide by two the number of interconnects between building blocks, it turns out that circuit designers use interconnect standards based on differential pairs such as PCIe, Infiniband, RapidIO, NVLink, etc. Doubling the number of binary signals is a better solution than using single-ended quaternary signals. The design of quaternary basic gates, adders and multipliers are compared with the corresponding binary ones. At each level, the transistor count ratio between quaternary and binary circuits is greater than the x2 information ratio between base 4 and base 2. Quaternary signaling is not a solution, either between or within circuit blocks .

cs.AR↗
arXiv2020

Comparing quaternary and binary multipliers

We compare the implementation of a 8x8 bit multiplier with two different implementations of a 4x4 quaternary digit multiplier. Interfacing this binary multiplier with quaternary to binary decoders and binary to quaternary encoders leads to a 4x4 multiplier that outperforms the best direct implementation of a 4x4 quaternary multiplier. The far greater complexity of the 1-digit multipliers and 1-digit adders used in this direct implementation compared to the binary 1-bit multipliers and full adders cannot be compensated by the reduced count of quaternary operators. As the best quaternary multiplier includes the corresponding binary one, it means that there is no opportunity to get less interconnects, less chip area, less power dissipation with the quaternary multiplier.

cs.AR↗
arXiv2020

Best implementations of quaternary adders

The implementation of a quaternary 1-digit adder composed of a 2-bit binary adder, quaternary to binary decoders and binary to quaternary encoders is compared with several recent implementations of quaternary adders. This simple implementation outperforms all other implementations using only one power supply. It is equivalent to the best other implementation using three power supplies. The best quaternary adder using a 2-bit binary adder, the interface circuits between quaternary and binary levels are just overhead compared to the binary adder. This result shows that the quaternary approach for adders use more transistors, more chip area and more power dissipation than the corresponding binary ones.

cs.AR↗
arXiv2019

Comparing ternary and binary adders and multipliers

While many papers have proposed implementations of ternary adders and ternary multipliers, no comparisons have generally been done with the corresponding binary ones. We compare the implementations of binary and ternary adders and multipliers with the same computing capability according to the basic blocks that are 1-bit and 1-trit adders and 1-bit and 1-trit multipliers. Then we compare the complexity of these basic blocks by using the same CNTFET technology to evaluate the overall complexity of N-bit adders and M-trit adders on one side, and NxN bit multipliers and MxM trits multipliers with M = N/IR (IR = log(3)/log(2) is the information ratio). While ternary adders and multipliers have less input and output connections and use less basic building blocks, the complexity of the ternary building blocks is too high and the ternary adders and multipliers cannot compete with the binary ones.

cs.AR↗
arXiv2019

Ternary circuits: why R=3 is not the Optimal Radix for Computation

A demonstration that e=2.718 rounded to 3 is the best radix for computation is disproved. The MOSFET-like CNTFET technology is used to compare inverters, Nand, adders, multipliers, D Flip-Flops and SRAM cells. The transistor count ratio between ternary and binary circuits is generally greater than the log(3)/log(2) information ratio. The only exceptions concern a circuit approach that combines two circuit drawbacks (an additional power supply and a circuit conflict between transistors) and only when it implements circuits based on the ternary inverter. For arithmetic circuits such as adders and multipliers, the ternary circuits are always outperformed by the binary ones using the same technology.

cs.AR↗
arXiv2019

Coprocessors: failures and successes

The appearance and disappearance of coprocessors by integration into the CPU, the success or failure of coprocessors are examined by summarizing their characteristics from the mainframes of the 1960s. The coprocessors most particularly reviewed are the IBM 360 and CDC-6600 I/O processors, the Intel 8087 math coprocessor, the Cell processor, the Intel Xeon Phi coprocessors, the GPUs, the FPGAs, and the coprocessors of manycores SW26010 and Pezy SC-2 used in high-ranked supercomputers in the TOP500 or Green500. The conditions for a coprocessor to be viable in the medium or long-term are defined.

cs.AR↗
arXiv2019

Evolution of Technologies and Multivalued Circuits

For more than 45 years, many multi-valued circuits have been presented. With very rare exceptions, they have been unsuccessful for fundamental reasons that can be explained. Each time a new circuit technology is presented, a lot of new MVL circuits are proposed. Can new circuit technologies overcome the fundamental disadvantages of MVL circuits? The evolution of IC technologies in the last decades unfortunately increases the disadvantage of MVL circuits versus binary ones. For non conventional technologies, only quantum devices look promising, even if implementation is challenging and applications are restricted to a small niche.

cs.ET↗