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Daniel Litinski

Publications and source records attributed to Daniel Litinski.

15 recordsLinked to original sources
arXiv2025

Blocklet concatenation: Low-overhead fault-tolerant protocols for fusion-based quantum computation

We introduce a construction for protocols for fault-tolerant quantum computing based on code concatenation and transversal gates. These protocols can be interpreted as families of quantum circuits of low-weight stabilizer measurements without strict locality constraints, effectively implementing concatenated codes. However, we primarily study these protocols in the context of photonic fusion-based quantum computing (FBQC), where they yield families of fusion networks with constant-sized resource states. Their high erasure thresholds relative to their resource-state cost establish them as promising candidates to replace surface codes in the context of FBQC. Examples include protocol families using 8-, 10- and 12-qubit resource states, with erasure thresholds of 13.8%, 19.1% and 11.5%, and footprint-per-logical-qubit scaling as $\mathcal{O}(d)$, $\mathcal{O}(d^{1.46})$ and $\mathcal{O}(d^{0.58})$, respectively, where $d$ is the code distance. We also present techniques for performing logical operations, decoding, and implementing the protocols in photonic hardware. Although we focus on photonic FBQC, these ideas may also be of interest in other settings.

quant-ph↗
arXiv2024

Quantum schoolbook multiplication with fewer Toffoli gates

This paper presents a method for constructing quantum circuits for schoolbook multiplication using controlled add-subtract circuits, asymptotically halving the Toffoli count compared to traditional controlled-adder-based constructions. Controlled n-qubit add-subtract circuits, which perform an addition when the control qubit is one and a subtraction when it is zero, require only n-1 Toffoli gates, instead of the 2n-1 needed for controlled adders. Despite the existence of multiplication circuits with better asymptotic scaling, schoolbook multiplication yields the lowest Toffoli counts for small register sizes, making it advantageous in practical applications. For example, the presented approach reduces the Toffoli count by up to around 30% in circuits for breaking 256-bit elliptic curve keys compared to circuits with standard schoolbook multipliers.

quant-ph↗
arXiv2023

How to compute a 256-bit elliptic curve private key with only 50 million Toffoli gates

We use Shor's algorithm for the computation of elliptic curve private keys as a case study for resource estimates in the silicon-photonics-inspired active-volume architecture. Here, a fault-tolerant surface-code quantum computer consists of modules with a logarithmic number of non-local inter-module connections, modifying the algorithmic cost function compared to 2D-local architectures. We find that the non-local connections reduce the cost per key by a factor of 300-700 depending on the operating regime. At 10% threshold, assuming a 10-$\mu$s code cycle and non-local connections, one key can be generated every 10 minutes using 6000 modules with 1152 physical qubits each. By contrast, a device with strict 2D-local connectivity requires more qubits and produces one key every 38 hours. We also find simple architecture-independent algorithmic modifications that reduce the Toffoli count per key by up to a factor of 5. These modifications involve reusing the stored state for multiple keys and spreading the cost of the modular division operation over multiple parallel instances of the algorithm.

quant-ph↗
arXiv2023

Unifying flavors of fault tolerance with the ZX calculus

There are several models of quantum computation which exhibit shared fundamental fault-tolerance properties. This article makes commonalities explicit by presenting these different models in a unifying framework based on the ZX calculus. We focus on models of topological fault tolerance - specifically surface codes - including circuit-based, measurement-based and fusion-based quantum computation, as well as the recently introduced model of Floquet codes. We find that all of these models can be viewed as different flavors of the same underlying stabilizer fault-tolerance structure, and sustain this through a set of local equivalence transformations which allow mapping between flavors. We anticipate that this unifying perspective will pave the way to transferring progress among the different views of stabilizer fault-tolerance and help researchers familiar with one model easily understand others.

quant-ph↗
arXiv2022

Active volume: An architecture for efficient fault-tolerant quantum computers with limited non-local connections

In existing general-purpose architectures for surface-code-based fault-tolerant quantum computers, the cost of a quantum computation is determined by the circuit volume, i.e., the number of qubits multiplied by the number of non-Clifford gates. We introduce an architecture using non-2D-local connections in which the cost does not scale with the number of qubits, and instead only with the number of logical operations. Each logical operation has an associated active volume, such that the cost of a quantum computation can be quantified as a sum of active volumes of all operations. For quantum computations with thousands of logical qubits, the active volume can be orders of magnitude lower than the circuit volume. Importantly, the architecture does not require all-to-all connectivity between N logical qubits. Instead, each logical qubit is connected to O(log N) other sites. As an example, we show that, using the same number of logical qubits, a 2048-bit factoring algorithm can be executed 44 times faster than on a general-purpose architecture without non-local connections. With photonic qubits, long-range connections are available and we show how photonic components can be used to construct a fusion-based active-volume quantum computer.

quant-ph↗
arXiv2021

Interleaving: Modular architectures for fault-tolerant photonic quantum computing

Useful fault-tolerant quantum computers require very large numbers of physical qubits. Quantum computers are often designed as arrays of static qubits executing gates and measurements. Photonic qubits require a different approach. In photonic fusion-based quantum computing (FBQC), the main hardware components are resource-state generators (RSGs) and fusion devices connected via waveguides and switches. RSGs produce small entangled states of a few photonic qubits, whereas fusion devices perform entangling measurements between different resource states, thereby executing computations. In addition, low-loss photonic delays such as optical fiber can be used as fixed-time quantum memories simultaneously storing thousands of photonic qubits. Here, we present a modular architecture for FBQC in which these components are combined to form "interleaving modules" consisting of one RSG with its associated fusion devices and a few fiber delays. Exploiting the multiplicative power of delays, each module can add thousands of physical qubits to the computational Hilbert space. Networks of modules are universal fault-tolerant quantum computers, which we demonstrate using surface codes and lattice surgery as a guiding example. Our numerical analysis shows that in a network of modules containing 1-km-long fiber delays, each RSG can generate four logical distance-35 surface-code qubits while tolerating photon loss rates above 2% in addition to the fiber-delay loss. We illustrate how the combination of interleaving with further uses of non-local fiber connections can reduce the cost of logical operations and facilitate the implementation of unconventional geometries such as periodic boundaries or stellated surface codes. Interleaving applies beyond purely optical architectures, and can also turn many small disconnected matter-qubit devices with transduction to photons into a large-scale quantum computer.

quant-ph↗
arXiv2019

Magic State Distillation: Not as Costly as You Think

Despite significant overhead reductions since its first proposal, magic state distillation is often considered to be a very costly procedure that dominates the resource cost of fault-tolerant quantum computers. The goal of this work is to demonstrate that this is not true. By writing distillation circuits in a form that separates qubits that are capable of error detection from those that are not, most logical qubits used for distillation can be encoded at a very low code distance. This significantly reduces the space-time cost of distillation, as well as the number of qubits. In extreme cases, it can cost less to distill a magic state than to perform a logical Clifford gate on full-distance logical qubits.

quant-ph↗
arXiv2018

Higher order topological superconductors as generators of quantum codes

We show that interactions can drive a class of higher order topological superconductors (HOTSC) into symmetry enriched topologically ordered phases exemplified by topological quantum error correcting codes. In two dimensions, interacting HOTSC realize various topologically ordered surface and color codes. In three dimensions, interactions can drive HOTSC protected by subsystem symmetries into recently discovered fracton phases. We explicitly relate fermion parity operators underlying the gapless excitations of the HOTSC to the Wilson algebra of symmetry enriched quantum codes. Arrays of crossed Majorana wires provide an experimental platform for realizing fracton matter and for probing the quantum phase transition between HOTSC and topologically ordered phase.

cond-mat.str-el↗
arXiv2018

A Game of Surface Codes: Large-Scale Quantum Computing with Lattice Surgery

Given a quantum gate circuit, how does one execute it in a fault-tolerant architecture with as little overhead as possible? In this paper, we discuss strategies for surface-code quantum computing on small, intermediate and large scales. They are strategies for space-time trade-offs, going from slow computations using few qubits to fast computations using many qubits. Our schemes are based on surface-code patches, which not only feature a low space cost compared to other surface-code schemes, but are also conceptually simple, simple enough that they can be described as a tile-based game with a small set of rules. Therefore, no knowledge of quantum error correction is necessary to understand the schemes in this paper, but only the concepts of qubits and measurements. As an example, assuming a physical error rate of $10^{-4}$ and a code cycle time of 1 $\mu$s, a classically intractable 100-qubit quantum computation with a $T$ count of $10^8$ and a $T$ depth of $10^6$ can be executed in 4 hours using 55,000 qubits, in 22 minutes using 120,000 qubits, or in 1 second using 330,000,000 qubits.

quant-ph↗
arXiv2018

Quantum Computing with Majorana Fermion Codes

We establish a unified framework for Majorana-based fault-tolerant quantum computation with Majorana surface codes and Majorana color codes. All logical Clifford gates are implemented with zero time overhead. This is done by introducing a protocol for Pauli product measurements with tetrons and hexons which only requires local 4-Majorana parity measurements. An analogous protocol is used in the fault-tolerant setting, where tetrons and hexons are replaced by Majorana surface code patches, and parity measurements are replaced by lattice surgery, still only requiring local few-Majorana parity measurements. To this end, we discuss twist defects in Majorana fermion surface codes and adapt the technique of twist-based lattice surgery to fermionic codes. Moreover, we propose a new family of codes that we refer to as Majorana color codes, which are obtained by concatenating Majorana surface codes with small Majorana fermion codes. Majorana surface and color codes can be used to decrease the space overhead and stabilizer weight compared to their bosonic counterparts.

cond-mat.mes-hall↗
arXiv2017

Lattice Surgery with a Twist: Simplifying Clifford Gates of Surface Codes

We present a planar surface-code-based scheme for fault-tolerant quantum computation which eliminates the time overhead of single-qubit Clifford gates, and implements long-range multi-target CNOT gates with a time overhead that scales only logarithmically with the control-target separation. This is done by replacing hardware operations for single-qubit Clifford gates with a classical tracking protocol. Inter-qubit communication is added via a modified lattice surgery protocol that employs twist defects of the surface code. The long-range multi-target CNOT gates facilitate magic state distillation, which renders our scheme fault-tolerant and universal.

quant-ph↗
arXiv2017

Braiding by Majorana Tracking and Long-Range CNOT Gates with Color Codes

Color-code quantum computation seamlessly combines Majorana-based hardware with topological error correction. Specifically, as Clifford gates are transversal in two-dimensional color codes, they enable the use of the Majoranas' nonabelian statistics for gate operations at the code level. Here, we discuss the implementation of color codes in arrays of Majorana nanowires that avoid branched networks such as T-junctions, thereby simplifying their realization. We show that, in such implementations, nonabelian statistics can be exploited without ever performing physical braiding operations. Physical braiding operations are replaced by Majorana tracking, an entirely software-based protocol which appropriately updates the Majoranas involved in the color-code stabilizer measurements. This approach minimizes the required hardware operations for single-qubit Clifford gates. For Clifford completeness, we combine color codes with surface codes, and use color-to-surface-code lattice surgery for long-range multi-target CNOT gates which have a time overhead that grows only logarithmically with the physical distance separating control and target qubits. With the addition of magic state distillation, our architecture describes a fault-tolerant universal quantum computer in systems such as networks of tetrons, hexons, or Majorana box qubits, but can also be applied to non-topological qubit platforms.

cond-mat.mes-hall↗
arXiv2017

Combining Topological Hardware and Topological Software: Color Code Quantum Computing with Topological Superconductor Networks

We present a scalable architecture for fault-tolerant topological quantum computation using networks of voltage-controlled Majorana Cooper pair boxes, and topological color codes for error correction. Color codes have a set of transversal gates which coincides with the set of topologically protected gates in Majorana-based systems, namely the Clifford gates. In this way, we establish color codes as providing a natural setting in which advantages offered by topological hardware can be combined with those arising from topological error-correcting software for full-fledged fault-tolerant quantum computing. We provide a complete description of our architecture including the underlying physical ingredients. We start by showing that in topological superconductor networks, hexagonal cells can be employed to serve as physical qubits for universal quantum computation, and present protocols for realizing topologically protected Clifford gates. These hexagonal cell qubits allow for a direct implementation of open-boundary color codes with ancilla-free syndrome readout and logical $T$-gates via magic state distillation. For concreteness, we describe how the necessary operations can be implemented using networks of Majorana Cooper pair boxes, and give a feasibility estimate for error correction in this architecture. Our approach is motivated by nanowire-based networks of topological superconductors, but could also be realized in alternative settings such as quantum Hall-superconductor hybrids.

cond-mat.mes-hall↗
arXiv2016

The Interacting Mesoscopic Capacitor Out of Equilibrium

We consider the full nonequilibrium response of a mesoscopic capacitor in the large transparency limit, exactly solving a model with electron-electron interactions appropriate for a cavity in the quantum Hall regime. For a cavity coupled to the electron reservoir via an ideal point contact, we show that the response to any time-dependent gate voltage $V_{\rm g}(t)$ is strictly linear in $V_{\rm g}$. We analyze the charge and current response to a sudden gate voltage shift, and find that this response is not captured by a simple circuit analogy. In particular, in the limit of strong interactions a sudden change in the gate voltage leads to the emission of a sequence of multiple charge pulses, the width and separation of which are controlled by the charge-relaxation time $\tau_{\rm c} = h C_{\rm g}/e^2$ and the time of flight $\tau_{\rm f}$. We also consider the effect of a finite reflection amplitude in the point contact, which leads to nonlinear-in-gate-voltage corrections to the charge and current response.

cond-mat.mes-hall↗