arXiv subjects

Darsen D. Lu

Publications and source records attributed to Darsen D. Lu.

5 recordsLinked to original sources

arXiv2023

CIMulator: A Comprehensive Simulation Platform for Computing-In-Memory Circuit Macros with Low Bit-Width and Real Memory Materials

This paper presents a simulation platform, namely CIMulator, for quantifying the efficacy of various synaptic devices in neuromorphic accelerators for different neural network architectures. Nonvolatile memory devices, such as resistive random-access memory, ferroelectric field-effect transistor, and volatile static random-access memory devices, can be selected as synaptic devices. A multilayer perceptron and convolutional neural networks (CNNs), such as LeNet-5, VGG-16, and a custom CNN named C4W-1, are simulated to evaluate the effects of these synaptic devices on the training and inference outcomes. The dataset used in the simulations are MNIST, CIFAR-10, and a white blood cell dataset. By applying batch normalization and appropriate optimizers in the training phase, neuromorphic systems with very low-bit-width or binary weights could achieve high pattern recognition rates that approach software-based CNN accuracy. We also introduce spiking neural networks with RRAM-based synaptic devices for the recognition of MNIST handwritten digits.

cs.NE↗

arXiv2022

Alleviation of Temperature Variation Induced Accuracy Degradation in Ferroelectric FinFET Based Neural Network

This paper reports the impacts of temperature variation on the inference accuracy of pre-trained all-ferroelectric FinFET deep neural networks, along with plausible design techniques to abate these impacts. We adopted a pre-trained artificial neural network (N.N.) with 96.4% inference accuracy on the MNIST dataset as the baseline. As an aftermath of temperature change, a compact model captured the conductance drift of a programmed cell over a wide range of gate biases. We observed a significant inference accuracy degradation in the analog neural network at 233 K for an N.N. trained at 300 K. Finally, we deployed binary neural networks with "read voltage" optimization to ensure immunity of N.N. to accuracy degradation under temperature variation, maintaining an inference accuracy of 96%. Keywords: Ferroelectric memories

cs.LG↗

arXiv2020

Formation of Uniform Crystal and Reduction of Electrical Variation in HfZrO$_2$ Ferroelectric Memory by Thermal Engineering

In this paper we proclaim excellent variation control in Hf$_{0.5}$Zr$_{0.5}$O$_2$ based ferroelectric films obtained by germination of large ferroelectric domain via extended duration of thermal annealing. 10nm thick Hf$_{0.5}$Zr$_{0.5}$O$_2$ based ferroelectric capacitors with TiN as bottom and top electrodes are fabricated and characterized. The duration of rapid thermal annealing (RTA) is varied to observe its effect on crystal formation and device electrical properties at 700C. The device to device variation in terms of coercive voltage and peak capacitance are reduced from 0.4V to 0.01V and from 2*$10^{-5}$nF/cm$^2$ to 4*$10^{-6}$nF/cm$^2$, respectively, by increasing the RTA duration. High resolution transmission electron micrograph clearly shows large and uniform ferroelectric domains with RTA of 180 seconds. Extended duration of RTA likely allows uniform crystal to form, which mitigates the stochasticity of the distribution of ferroelectric and paraelectric domains, and deterministic switching has been infused. This improvement paves the way for implementing Hf$_{0.5}$Zr$_{0.5}$O$_2$ based deeply scaled devices for memory and steep slope device applications.

physics.app-ph↗

arXiv2020

Compact Device Models for FinFET and Beyond

Compact device models play a significant role in connecting device technology and circuit design. BSIM-CMG and BSIM-IMG are industry standard compact models suited for the FinFET and UTBB technologies, respectively. Its surface potential based modeling framework and symmetry preserving properties make them suitable for both analog/RF and digital design. In the era of artificial intelligence / deep learning, compact models further enhanced our ability to explore RRAM and other NVM-based neuromorphic circuits. We have demonstrated simulation of RRAM neuromorphic circuits with Verilog-A based compact model at NCKU. Further abstraction with macromodels is performed to enable larger scale machine learning simulation.

cs.ET↗

arXiv2020

A computationally efficient compact model for ferroelectric FETs for the simulation of online training of neural networks

Tri-gate ferroelectric FETs with Hf0.5Zr0.5O2 gate insulator for memory and neuromorphic applications are fabricated and characterized for multi-level operation. The conductance and threshold voltage exhibit highly linear and symmetric characteristics. A compact analytical model is developed to accurately capture FET transfer characteristics, including series resistance, coulombic scattering, and vertical field dependent mobility degradation effects, as well as the evolvement of threshold voltage and mobility with ferroelectric polarization switching. The model covers both sub-threshold and strong inversion operation. Additional measurements confirm ferroelectric switching as opposed to carrier-trapping-based memory operation. The compact model is implemented in a simulation platform for online training of deep neural networks.

physics.app-ph↗