arXiv subjects

Darsen Lu

Publications and source records attributed to Darsen Lu.

4 recordsLinked to original sources

arXiv2025

Quantum-Chiplet: A Novel Python-Based Efficient and Scalable Design Methodology for Quantum Circuit Verification and Implementation

Analysis and verification of quantum circuits are highly challenging, given the exponential dependence of the number of states on the number of qubits. For analytical derivation, we propose a new quantum polynomial representation (QPR) to facilitate the analysis of massively parallel quantum computation and detect subtle errors. For the verification of quantum circuits, we introduce Quantum-Chiplet, a hierarchical quantum behavior modeling methodology that facilitates rapid integration and simulation. Each chiplet is systematically transformed into quantum gates. For circuits involving n qubits and k quantum gates, the design complexity is reduced from "greater than O(2^n)" to O(k). This approach provides an open-source solution, enabling a highly customized solution for quantum circuit simulation within the native Python environment, thereby reducing reliance on traditional simulation packages. A quantum amplitude estimation example demonstrates that this method significantly improves the design process, with more than 10x speed-up compared to IBM Qiskit at 14 qubits.

quant-ph↗

arXiv2022

Neuromorphic Computing with Ferroelectric FinFETs in the Presence of Temperature, Process Variation, Device Aging and Flicker Noise

This paper reports a comprehensive study on the impacts of temperature-change, process variation, flicker noise and device aging on the inference accuracy of pre-trained all-ferroelectric (FE) FinFET deep neural networks. Multiple-level-cell (MLC) operation with a novel adaptive-program-and-read algorithm with 100ns write pulse has been experimentally demonstrated in 5 nm thick hafnium zirconium oxide (HZO)-based FE-FinFET. With pre-trained neural network (NN) with 97.5% inference accuracy on MNIST dataset as baseline, device to device variation is shown to have negligible impact. Flicker noise characterization at various bias conditions depicts that drain current fluctuation is less than 0.7% with virtually no inference accuracy degradation. The conductance drift of a programmed cell, as an aftermath of temperature change, was captured by a compact model over a wide range of gate biases. Despite significant inference accuracy degradation at 233K for a NN trained at 300K, gate bias optimization for recovering the accuracy is demonstrated. Endurance above 10$^8$ cycles and extrapolated retention above 10 years are shown, which paves the way for edge device artificial intelligence with FE-FinFETs.

cs.ET↗

arXiv2021

Stochastic Variations in Nanoscale HZO based Ferroelectric finFETs: A Synergistic Approach of READ Optimization and Hybrid Precision Mixed Signal WRITE Operation to Mitigate the Implications on DNN Applications

This paper reports a synergistic approach of READ and WRITE optimization by deploying a high-precision digital computation unit along with a low-precision ferroelectric finFET (Fe-finFETs) based analog vector-matrix multiplication block for mitigating the impact of stochastic device variations in hafnium zirconium oxide (HZO) based Fe-finFETs.

physics.app-ph↗

arXiv2021

Analytical Modelling of Ferroelectricity Instigated Enhanced Electrostatic Control in Short-Channel FinFETs

This study simulated negative-capacitance double gate FinFETs with channel lengths ranging from 25nm to 100nm using TCAD. The results show that negative capacitance significantly reduces subthreshold swing as well as drain induced barrier lowering effects. The improvement is found to be significantly more prominent for short channel devices than long ones, which demonstrates the tremendous advantage of negative capacitance gate stack for scaled MOSFETs. A compact analytical formulation is developed to quantify sub-threshold swing improvement for short channel devices.

physics.app-ph↗