arXiv subjects

David Bol

Publications and source records attributed to David Bol.

18 recordsLinked to original sources

arXiv2026

UNCASExt -- A Systematic Computational Framework for Uncertainty Propagation and Scope Consistency in Absolute Environmental Sustainability Assessments (AESA)

Absolute environmental sustainability assessment (AESA) has gained increasing attention in environmental research and policymaking. However, its reliability is challenged by several sources of uncertainty that remain insufficiently accounted for, as well as by scope inconsistencies within the absolute sustainability ratio (ASR), which compares estimated environmental burdens with allocated carrying capacities for a given human activity. This work introduces UNCASExt, an extension of the UNCASE framework for systematically propagating uncertainty and ensuring scope consistency in AESA, together with a supporting open-source Python package, pyaesa. At country and sector levels, the computational framework formalizes allocation procedures that match the scope of allocated carrying capacities with that of estimated environmental burdens across three dimensions: impact pathway modeling; production-based versus consumption-based accounting; business-to-consumer versus business-to-business activities. It also incorporates temporal dynamics, supporting both retrospective and prospective assessments with either static steady-state or dynamic carrying capacities, including greenhouse gas budgets from the Intergovernmental Panel on Climate Change Sixth Assessment Report under Shared Socioeconomic Pathway transition scenarios. The framework is applied to a case study of electricity consumption in France over the period 2019 to 2060. The results show that mismatches between the functional units of estimated environmental burdens and allocated carrying capacities can lead to substantial underallocation, with a median factor of 4.6x across all available sector-region pairs in EXIOBASE 3.10.2. Overall, UNCASExt and pyaesa provide a scalable solution to support AESA harmonization and a versatile way forward to bridge the gap between methodological guidelines and practical application.

cs.CY↗

arXiv2025

Purer than pure: how purity reshapes the upstream materiality of the semiconductor industry

Growing attention is given to the environmental impacts of the digital sector, exacerbated by the increase of digital products and services in our globalized societies. The materiality of the digital sector is often presented through the environmental impacts of mining activities to point out that digitization does not mean dematerialization. Despite its importance, such a narrative is often restricted to a few minerals (e.g., cobalt, lithium) that have become the symbols of extractive industries. In this paper, we further explore the materiality of the digital sector with an approach based on the diversity of elements and their purity requirements in the semiconductor industry. Semiconductors are responsible for manufacturing the key building blocks of the digital sector, i.e., microchips. Given that the need for ultra-high purity materials is very specific to the semiconductor industry, a few companies around the world have been studied, revealing new critical actors in complex supply chains. This highlights strong dependencies towards other industrial sectors with mass production and the need for a deeper investigation of interactions with the chemical industry, complementary to the mining industry.

cs.CY↗

arXiv2024

IMAGINE: An 8-to-1b 22nm FD-SOI Compute-In-Memory CNN Accelerator With an End-to-End Analog Charge-Based 0.15-8POPS/W Macro Featuring Distribution-Aware Data Reshaping

Charge-domain compute-in-memory (CIM) SRAMs have recently become an enticing compromise between computing efficiency and accuracy to process sub-8b convolutional neural networks (CNNs) at the edge. Yet, they commonly make use of a fixed dot-product (DP) voltage swing, which leads to a loss in effective ADC bits due to data-dependent clipping or truncation effects that waste precious conversion energy and computing accuracy. To overcome this, we present IMAGINE, a workload-adaptive 1-to-8b CIM-CNN accelerator in 22nm FD-SOI. It introduces a 1152x256 end-to-end charge-based macro with a multi-bit DP based on an input-serial, weight-parallel accumulation that avoids power-hungry DACs. An adaptive swing is achieved by combining a channel-wise DP array split with a linear in-ADC implementation of analog batch-normalization (ABN), obtaining a distribution-aware data reshaping. Critical design constraints are relaxed by including the post-silicon equivalent noise within a CIM-aware CNN training framework. Measurement results showcase an 8b system-level energy efficiency of 40TOPS/W at 0.3/0.6V, with competitive accuracies on MNIST and CIFAR-10. Moreover, the peak energy and area efficiencies of the 187kB/mm2 macro respectively reach up to 0.15-8POPS/W and 2.6-154TOPS/mm2, scaling with the 8-to-1b computing precision. These results exceed previous charge-based designs by 3-to-5x while being the first work to provide linear in-memory rescaling.

cs.AR↗

arXiv2024

MANTIS: A Mixed-Signal Near-Sensor Convolutional Imager SoC Using Charge-Domain 4b-Weighted 5-to-84-TOPS/W MAC Operations for Feature Extraction and Region-of-Interest Detection

Recent advances in artificial intelligence have prompted the search for enhanced algorithms and hardware to support the deployment of machine learning at the edge. More specifically, in the context of the Internet of Things (IoT), vision chips must be able to fulfill tasks of low to medium complexity, such as feature extraction or region-of-interest (RoI) detection, with a sub-mW power budget imposed by the use of small batteries or energy harvesting. Mixed-signal vision chips relying on in- or near-sensor processing have emerged as an interesting candidate, thanks to their favorable tradeoff between energy efficiency (EE) and computational accuracy compared to digital systems for these specific tasks. In this paper, we introduce a mixed-signal convolutional imager system-on-chip (SoC) codenamed MANTIS, featuring a unique combination of large 16$\times$16 4b-weighted filters, operation at multiple scales, and double sampling, well suited to the requirements of medium-complexity tasks. The main contributions are (i) circuits called DS3 units combining delta-reset sampling, image downsampling, and voltage downshifting, and (ii) charge-domain multiply-and-accumulate (MAC) operations based on switched-capacitor amplifiers and charge sharing in the capacitive DAC of the successive-approximation ADCs. MANTIS achieves peak EEs normalized to 1b operations of 4.6 and 84.1 TOPS/W at the accelerator and SoC levels, while computing feature maps with a root mean square error ranging from 3 to 11.3$\%$. It also demonstrates a face RoI detection with a false negative rate of 11.5$\%$, while discarding 81.3$\%$ of image patches and reducing the data transmitted off chip by 13$\times$ compared to the raw image.

cs.AR↗

arXiv2024

A nA-Range Area-Efficient Sub-100-ppm/{\deg}C Peaking Current Reference Using Forward Body Biasing in 0.11-$\mu$m Bulk and 22-nm FD-SOI

In recent years, the development of the Internet of Things (IoT) has prompted the search for nA-range current references that are simultaneously constrained to a small area and robust to process, voltage and temperature variations. Yet, such references have remained elusive, as existing architectures fail to reach a low temperature coefficient (TC) while minimizing silicon area. In this work, we propose a nA-range constant-with-temperature (CWT) peaking current reference, in which a resistor is biased by the threshold voltage difference between two transistors in weak inversion. This bias voltage is lower than in conventional architectures to cut down the silicon area occupied by the resistor and is obtained by forward body biasing one of the two transistors with an ultra-low-power voltage reference so as to reduce its threshold voltage. In addition, the proposed reference includes a circuit to suppress the leakage of parasitic diodes at high temperature, and two simple trimming mechanisms for the reference current and its TC. As the proposed design relies on the body effect, it has been validated in both 0.11-$\mu$m bulk and 22-nm fully-depleted silicon-on-insulator, to demonstrate feasibility across different technology types. In post-layout simulation, the 0.11-$\mu$m design generates a 5-nA current with a 65-ppm/{\deg}C TC and a 2.84-%/V line sensitivity (LS), while in measurement, the 22-nm design achieves a 1.5-nA current with an 89-ppm/{\deg}C TC and a 0.51-%/V LS. As a result of the low resistor bias voltage, the proposed references occupy a silicon area of 0.00954 mm$^2$ in 0.11 $\mu$m (resp. 0.00214 mm$^2$ in 22 nm) at least 1.8$\times$ (resp. 8.2$\times$) smaller than fabricated nA-range CWT references, but with a TC improved by 6.1$\times$ (resp. 4.4$\times$).

cs.AR↗

arXiv2024

A 2.5-nA Area-Efficient Temperature-Independent 176-/82-ppm/{\deg}C CMOS-Only Current Reference in 0.11-$\mu$m Bulk and 22-nm FD-SOI

Internet-of-Things (IoT) applications require nW-power current references that are robust to process, voltage and temperature (PVT) variations, to maintain the performance of IoT sensor nodes in a wide range of operating conditions. However, nA-range current references are rarely area-efficient due to the use of large gate-leakage transistors or resistors, which occupy a significant silicon area at this current level. In this paper, we introduce a nA-range constant-with-temperature (CWT) current reference, relying on a self-cascode MOSFET (SCM) biased by a four-transistor ultra-low-power voltage reference through a single-transistor buffer. The proposed reference includes a temperature coefficient (TC) calibration mechanism to maintain performance across process corners. In addition, as the proposed design relies on the body effect, it has been fabricated and measured in 0.11-$\mu$m bulk and 22-nm fully-depleted silicon-on-insulator (FD-SOI) to demonstrate feasibility in both technology types. On the one hand, the 0.11-$\mu$m design consumes a power of 16.8 nW at 1.2 V and achieves a 2.3-nA current with a line sensitivity (LS) of 2.23 %/V at 25{\deg}C and a TC of 176 ppm/{\deg}C at 1.2 V from -40 to 85{\deg}C. On the other hand, the 22-nm design consumes a power of 16.3 nW at 1.5 V and achieves a 2.5-nA current with a 1.53-%/V LS at 25{\deg}C and an 82-ppm/{\deg}C TC at 1.5 V from -40 to 85{\deg}C. Thanks to their simple architecture, the proposed references achieve a silicon area of 0.0106 mm$^2$ in 0.11 $\mu$m and 0.0026 mm$^2$ in 22 nm without compromising other figures of merit, and are thus competitive with state-of-the-art CWT references operating in the same current range.

cs.AR↗

arXiv2024

A Cradle-to-Gate Life Cycle Analysis of Bitcoin Mining Equipment Using Sphera LCA and ecoinvent Databases

Bitcoin mining is regularly pointed out for its massive energy consumption and associated greenhouse gas emissions, hence contributing significantly to climate change. However, most studies ignore the environmental impacts of producing mining equipment, which is problematic given the short lifespan of such highly specific hardware. In this study, we perform a cradle-to-gate life cycle assessment (LCA) of dedicated Bitcoin mining equipment, considering their specific architecture. Our results show that the application-specific integrated circuit designed for Bitcoin mining is the main contributor to production-related impacts. This observation applies to most impact categories, including the global warming potential. In addition, this finding stresses out the necessity to carefully consider the specificity of the hardware. By comparing these results with several usage scenarios, we also demonstrate that the impacts of producing this type of equipment can be significant (up to 80% of the total life cycle impacts), depending on the sources of electricity supply for the use phase. Therefore, we highlight the need to consider the production phase when assessing the environmental impacts of Bitcoin mining hardware. To test the validity of our results, we use the Sphera LCA and ecoinvent databases for the background modeling of our system. Surprisingly, it leads to results with variations of up to 4 orders of magnitude for toxicity-related indicators, despite using the same foreground modeling. This database mismatch phenomenon, already identified in previous studies, calls for better understanding, consideration and discussion of environmental impacts in the field of electronics, going well beyond climate change indicators.

cs.CY↗

arXiv2023

A 1.1- / 0.9-nA Temperature-Independent 213- / 565-ppm/$^\circ$C Self-Biased CMOS-Only Current Reference in 65-nm Bulk and 22-nm FDSOI

In many applications, the ability of current references to cope with process, voltage, and temperature (PVT) variations is critical to maintaining system-level performance. However, temperature-independent current references operating in the nA range are rarely area-efficient due to the use of large resistors which occupy a significant silicon area at this current level. In this article, we introduce a nA-range constant-with-temperature (CWT) current reference relying on a self-cascode MOSFET (SCM), biased by a proportional-to-absolute-temperature (PTAT) voltage with a CWT offset. On the one hand, the proposed reference has been simulated post-layout in 65-nm bulk. This design consumes 5.4 nW at 0.7 V and achieves a 1.1-nA current with a line sensitivity (LS) of 0.69 %/V and a temperature coefficient (TC) of 213 ppm/$^\circ$C. On the other hand, the proposed reference has been simulated and fabricated in 22-nm fully depleted silicon-on-insulator (FDSOI). This second design requires additional features to mitigate the impact of parasitic diode leakage at high temperature. In measurement, it consumes 5.8 nW at 0.9 V and achieves a 0.9-nA current with a 0.39-%/V LS and a 565-ppm/$^\circ$C TC. As a result of using an SCM, the proposed references occupy a silicon area of 0.0021 mm$^2$ in 65 nm (respectively, 0.0132 mm$^2$ in 22 nm) at least 25$\times$ (respectively, 4$\times$) smaller than state-of-the-art CWT references operating in the same current range.

cs.AR↗

arXiv2022

From Silicon Shield to Carbon Lock-in ? The Environmental Footprint of Electronic Components Manufacturing in Taiwan (2015-2020)

Taiwan plans to rapidly increase its industrial production capacity of electronic components while concurrently setting policies for its ecological transition. Given that the island is responsible for the manufacturing of a significant part of worldwide electronics components, the sustainability of the Taiwanese electronics industry is therefore of critical interest. In this paper, we survey the environmental footprint of 16 Taiwanese electronic components manufacturers (ECM) using corporate sustainability responsibility reports (CSR). Based on data from 2015 to 2020, this study finds out that our sample of 16 manufacturers increased its greenhouse gases (GHG) emissions by 7.5\% per year, its final energy and electricity consumption by 8.8\% and 8.9\%, and the water usage by 6.1\%. We show that the volume of manufactured electronic components and the environmental footprints compiled in this study are strongly correlated, which suggests that relative efficiency gains are not sufficient to curb the environmental footprint at the national scale. Given the critical nature of electronics industry for Taiwan's geopolitics and economics, the observed increase of energy consumption and the slow renewable energy roll-out, these industrial activities could create a carbon lock-in, blocking the Taiwanese government from achieving its carbon reduction goals and its sustainability policies. Besides, the European Union, the USA or even China aim at developing an industrial ecosystem targeting sub-10nm CMOS technology nodes similar to Taiwan. This study thus provides important insights regarding the environmental implications associated with such a technology roadmap. All data and calculation models used in this study are provided as supplementary material.

cs.CY↗

arXiv2022

A Family of Current References Based on 2T Voltage References: Demonstration in 0.18-$\mu$m with 0.1-nA PTAT and 1.1-$\mu$A CWT 38-ppm/$^\circ$C Designs

The robustness of current and voltage references to process, voltage and temperature (PVT) variations is paramount to the operation of integrated circuits in real-world conditions. However, while recent voltage references can meet most of these requirements with a handful of transistors, current references remain rather complex, requiring significant design time and silicon area. In this paper, we present a family of simple current references consisting of a two-transistor (2T) ultra-low-power voltage reference, buffered onto a voltage-to-current converter by a single transistor. Two topologies are fabricated in a 0.18-$\mu$m partially-depleted silicon-on-insulator (SOI) technology and measured over 10 dies. First, a 7T nA-range proportional-to-absolute-temperature (PTAT) reference intended for constant-$g_m$ biasing of subthreshold operational amplifiers demonstrates a 0.096-nA current with a line sensitivity (LS) of 1.48 %/V, a temperature coefficient (TC) of 0.75 %/$^\circ$C, and a variability $(\sigma/\mu)$ of 1.66 %. Then, two 4T+1R $\mu$A-range constant-with-temperature (CWT) references with (resp. without) TC calibration exhibit a 1.09-$\mu$A (resp. 0.99-$\mu$A) current with a 0.21-%/V (resp. 0.20-%/V) LS, a 38-ppm/$^\circ$C (resp. 290-ppm/$^\circ$C) TC, and a 0.87-% (resp. 0.65-%) $(\sigma/\mu)$. In addition, portability to common scaled CMOS technologies, such as 65-nm bulk and 28-nm fully-depleted SOI, is discussed and validated through post-layout simulations.

cs.AR↗

arXiv2021

Implementing a LoRa Software-Defined Radio on a General-Purpose ULP Microcontroller

Emerging Internet-of-Things sensing applications rely on ultra low-power (ULP) microcontroller units (MCUs) that wirelessly transmit data to the cloud. Typical MCUs nowadays consist of generic blocks, except for the protocol-specific radios implemented in hardware. Hardware radios however slow down the evolution of wireless protocols due to retrocompatiblity concerns. In this work, we explore a software-defined radio architecture by demonstrating a LoRa transceiver running on custom ULP MCU codenamed SleepRider with an ARM Cortex-M4 CPU. In SleepRider MCU, we offload the generic baseband operations (e.g., low-pass filtering) to a reconfigurable digital front-end block and use the Cortex-M4 CPU to perform the protocol-specific computations. Our software implementation of the LoRa physical layer only uses the native SIMD instructions of the Cortex-M4 to achieve real-time transmission and reception of LoRa packets. SleepRider MCU has been fabricated in a 28nm FDSOI CMOS technology and is used in a testbed to experimentally validate the software implementation. Experimental results show that the proposed software-defined radio requires only a CPU frequency of 20 MHz to correctly receive a LoRa packet, with an ultra-low power consumption of 0.42 mW on average.

eess.SP↗

arXiv2021

Bottom-up and top-down approaches for the design of neuromorphic processing systems: Tradeoffs and synergies between natural and artificial intelligence

While Moore's law has driven exponential computing power expectations, its nearing end calls for new avenues for improving the overall system performance. One of these avenues is the exploration of alternative brain-inspired computing architectures that aim at achieving the flexibility and computational efficiency of biological neural processing systems. Within this context, neuromorphic engineering represents a paradigm shift in computing based on the implementation of spiking neural network architectures in which processing and memory are tightly co-located. In this paper, we provide a comprehensive overview of the field, highlighting the different levels of granularity at which this paradigm shift is realized and comparing design approaches that focus on replicating natural intelligence (bottom-up) versus those that aim at solving practical artificial intelligence applications (top-down). First, we present the analog, mixed-signal and digital circuit design styles, identifying the boundary between processing and memory through time multiplexing, in-memory computation, and novel devices. Then, we highlight the key tradeoffs for each of the bottom-up and top-down design approaches, survey their silicon implementations, and carry out detailed comparative analyses to extract design guidelines. Finally, we identify necessary synergies and missing elements required to achieve a competitive advantage for neuromorphic systems over conventional machine-learning accelerators in edge computing applications, and outline the key ingredients for a framework toward neuromorphic intelligence.

cs.NE↗

arXiv2021

Assessing the embodied carbon footprint of IoT edge devices with a bottom-up life-cycle approach

In upcoming years, the number of Internet-of-Things (IoT) devices is expected to surge up to tens of billions of physical objects. However, while the IoT is often presented as a promising solution to tackle environmental challenges, the direct environmental impacts generated over the life cycle of the physical devices are usually overlooked. It is implicitly assumed that their environmental burden is negligible compared to the positive impacts they can generate. In this paper, we present a parametric framework based on hardware profiles to evaluate the cradle-to-gate carbon footprint of IoT edge devices. We exploit our framework in three ways. First, we apply it on four use cases to evaluate their respective production carbon footprint. Then, we show that the heterogeneity inherent to IoT edge devices must be considered as the production carbon footprint between simple and complex devices can vary by a factor of more than 150x. Finally, we estimate the absolute carbon footprint induced by the worldwide production of IoT edge devices through a macroscopic analysis over a 10-year period. Results range from 22 to 562 MtCO2-eq/year in 2027 depending on the deployment scenarios. However, the truncation error acknowledged for LCA bottom-up approaches usually lead to an undershoot of the environmental impacts. We compared the results of our use cases with the few reports available from Google and Apple, which suggest that our estimates could be revised upwards by a factor around 2x to compensate for the truncation error. Worst-case scenarios in 2027 would therefore reach more than 1000 MtCO2-eq/year. This truly stresses the necessity to consider environmental constraints when designing and deploying IoT edge devices.

cs.CY↗

arXiv2020

A 28-nm Convolutional Neuromorphic Processor Enabling Online Learning with Spike-Based Retinas

In an attempt to follow biological information representation and organization principles, the field of neuromorphic engineering is usually approached bottom-up, from the biophysical models to large-scale integration in silico. While ideal as experimentation platforms for cognitive computing and neuroscience, bottom-up neuromorphic processors have yet to demonstrate an efficiency advantage compared to specialized neural network accelerators for real-world problems. Top-down approaches aim at answering this difficulty by (i) starting from the applicative problem and (ii) investigating how to make the associated algorithms hardware-efficient and biologically-plausible. In order to leverage the data sparsity of spike-based neuromorphic retinas for adaptive edge computing and vision applications, we follow a top-down approach and propose SPOON, a 28-nm event-driven CNN (eCNN). It embeds online learning with only 16.8-% power and 11.8-% area overheads with the biologically-plausible direct random target projection (DRTP) algorithm. With an energy per classification of 313nJ at 0.6V and a 0.32-mm$^2$ area for accuracies of 95.3% (on-chip training) and 97.5% (off-chip training) on MNIST, we demonstrate that SPOON reaches the efficiency of conventional machine learning accelerators while embedding on-chip learning and being compatible with event-based sensors, a point that we further emphasize with N-MNIST benchmarking.

cs.NE↗

arXiv2019

A Low-Complexity LoRa Synchronization Algorithm Robust to Sampling Time Offsets

LoRaWAN is nowadays one of the most popular protocols for low-power Internet-of-Things communications. Although its physical layer, namely LoRa, has been thoroughly studied in the literature, aspects related to the synchronization of LoRa receivers have received little attention so far. The estimation and correction of carrier frequency and sampling time offsets is however crucial to attain the low sensitivity levels offered by the LoRa spread-spectrum modulation. The goal of this paper is to build a low-complexity, yet efficient synchronization algorithm capable of correcting both offsets. To this end, a complete analytical model of a LoRa signal corrupted by these offsets is first derived. Using this model, we propose a new estimator for the sampling time offset. We also show that the estimations of the carrier frequency and the sampling time offsets cannot be performed independently. Therefore, to avoid a complex joint estimation of both offsets, an iterative low-complexity synchronization algorithm is proposed. To reach a packet error rate of 10^-3, performance evaluations show that the proposed receiver requires only 1 or 2 dB higher SNR than a theoretical perfectly synchronized receiver, while incurring a very low computational overhead.

eess.SP↗

arXiv2019

Learning without feedback: Fixed random learning signals allow for feedforward training of deep neural networks

While the backpropagation of error algorithm enables deep neural network training, it implies (i) bidirectional synaptic weight transport and (ii) update locking until the forward and backward passes are completed. Not only do these constraints preclude biological plausibility, but they also hinder the development of low-cost adaptive smart sensors at the edge, as they severely constrain memory accesses and entail buffering overhead. In this work, we show that the one-hot-encoded labels provided in supervised classification problems, denoted as targets, can be viewed as a proxy for the error sign. Therefore, their fixed random projections enable a layerwise feedforward training of the hidden layers, thus solving the weight transport and update locking problems while relaxing the computational and memory requirements. Based on these observations, we propose the direct random target projection (DRTP) algorithm and demonstrate that it provides a tradeoff between accuracy and computational cost that is suitable for adaptive edge computing devices.

stat.ML↗

arXiv2019

MorphIC: A 65-nm 738k-Synapse/mm$^2$ Quad-Core Binary-Weight Digital Neuromorphic Processor with Stochastic Spike-Driven Online Learning

Recent trends in the field of neural network accelerators investigate weight quantization as a means to increase the resource- and power-efficiency of hardware devices. As full on-chip weight storage is necessary to avoid the high energy cost of off-chip memory accesses, memory reduction requirements for weight storage pushed toward the use of binary weights, which were demonstrated to have a limited accuracy reduction on many applications when quantization-aware training techniques are used. In parallel, spiking neural network (SNN) architectures are explored to further reduce power when processing sparse event-based data streams, while on-chip spike-based online learning appears as a key feature for applications constrained in power and resources during the training phase. However, designing power- and area-efficient spiking neural networks still requires the development of specific techniques in order to leverage on-chip online learning on binary weights without compromising the synapse density. In this work, we demonstrate MorphIC, a quad-core binary-weight digital neuromorphic processor embedding a stochastic version of the spike-driven synaptic plasticity (S-SDSP) learning rule and a hierarchical routing fabric for large-scale chip interconnection. The MorphIC SNN processor embeds a total of 2k leaky integrate-and-fire (LIF) neurons and more than two million plastic synapses for an active silicon area of 2.86mm$^2$ in 65nm CMOS, achieving a high density of 738k synapses/mm$^2$. MorphIC demonstrates an order-of-magnitude improvement in the area-accuracy tradeoff on the MNIST classification task compared to previously-proposed SNNs, while having no penalty in the energy-accuracy tradeoff.

cs.NE↗

arXiv2018

A 0.086-mm$^2$ 12.7-pJ/SOP 64k-Synapse 256-Neuron Online-Learning Digital Spiking Neuromorphic Processor in 28nm CMOS

Shifting computing architectures from von Neumann to event-based spiking neural networks (SNNs) uncovers new opportunities for low-power processing of sensory data in applications such as vision or sensorimotor control. Exploring roads toward cognitive SNNs requires the design of compact, low-power and versatile experimentation platforms with the key requirement of online learning in order to adapt and learn new features in uncontrolled environments. However, embedding online learning in SNNs is currently hindered by high incurred complexity and area overheads. In this work, we present ODIN, a 0.086-mm$^2$ 64k-synapse 256-neuron online-learning digital spiking neuromorphic processor in 28nm FDSOI CMOS achieving a minimum energy per synaptic operation (SOP) of 12.7pJ. It leverages an efficient implementation of the spike-driven synaptic plasticity (SDSP) learning rule for high-density embedded online learning with only 0.68$\mu$m$^2$ per 4-bit synapse. Neurons can be independently configured as a standard leaky integrate-and-fire (LIF) model or as a custom phenomenological model that emulates the 20 Izhikevich behaviors found in biological spiking neurons. Using a single presentation of 6k 16$\times$16 MNIST training images to a single-layer fully-connected 10-neuron network with on-chip SDSP-based learning, ODIN achieves a classification accuracy of 84.5% while consuming only 15nJ/inference at 0.55V using rank order coding. ODIN thus enables further developments toward cognitive neuromorphic devices for low-power, adaptive and low-cost processing.

cs.ET↗