arXiv subjects

David Rodriguez Perez

Publications and source records attributed to David Rodriguez Perez.

4 recordsLinked to original sources

arXiv2023

Autonomous error correction of a single logical qubit using two transmons

Large-scale quantum computers will inevitably need quantum error correction to protect information against decoherence. Traditional error correction typically requires many qubits, along with high-efficiency error syndrome measurement and real-time feedback. Autonomous quantum error correction (AQEC) instead uses steady-state bath engineering to perform the correction in a hardware-efficient manner. We realize an AQEC scheme, implemented with only two transmon qubits in a 2D scalable architecture, that actively corrects single-photon loss and passively suppresses low-frequency dephasing using six microwave drives. Compared to uncorrected encoding, factors of 2.0, 5.1, and 1.4 improvements are experimentally witnessed for the logical zero, one, and superposition states. Our results show the potential of implementing hardware-efficient AQEC to enhance the reliability of a transmon-based quantum information processor.

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arXiv2022

Hardware optimized parity check gates for superconducting surface codes

Error correcting codes use multi-qubit measurements to realize fault-tolerant quantum logic steps. In fact, the resources needed to scale-up fault-tolerant quantum computing hardware are largely set by this task. Tailoring next-generation processors for joint measurements, therefore, could result in improvements to speed, accuracy, or cost -- accelerating the development large-scale quantum computers. Here, we motivate such explorations by analyzing an unconventional surface code based on multi-body interactions between superconducting transmon qubits. Our central consideration, Hardware Optimized Parity (HOP) gates, achieves stabilizer-type measurements through simultaneous multi-qubit conditional phase accumulation. Despite the multi-body effects that underpin this approach, our estimates of logical faults suggest that this design can be at least as robust to realistic noise as conventional designs. We show a higher threshold of $1.25 \times 10^{-3}$ compared to the standard code's $0.79 \times 10^{-3}$. However, in the HOP code the logical error rate decreases more slowly with decreasing physical error rate. Our results point to a fruitful path forward towards extending gate-model platforms for error correction at the dawn of its empirical development.

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arXiv2021

Error-divisible two-qubit gates

We introduce a simple, widely applicable formalism for designing "error-divisible" two qubit gates: a quantum gate set where fractional rotations have proportionally reduced error compared to the full entangling gate. In current noisy intermediate-scale quantum (NISQ) algorithms, performance is largely constrained by error proliferation at high circuit depths, of which two-qubit gate error is generally the dominant contribution. Further, in many hardware implementations, arbitrary two qubit rotations must be composed from multiple two-qubit stock gates, further increasing error. This work introduces a set of criteria, and example waveforms and protocols to satisfy them, using superconducting qubits with tunable couplers for constructing continuous gate sets with significantly reduced error for small-angle rotations. If implemented at scale, NISQ algorithm performance would be significantly improved by our error-divisible gate protocols.

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arXiv2020

Improved autonomous error correction using variable dissipation in small logical qubit architectures

Coherence times for superconducting qubits have greatly improved over time. Moreover, small logical qubit architectures using engineered dissipation have shown great promise for further improvements in the coherence of a logical qubit manifold comprised of few physical qubits. Nevertheless, optimal working parameters for small logical qubits are generally not well understood. This work presents several approaches to finding preferential parameter configurations by looking at three different cases of increasing complexity. We begin by looking at state stabilization of a single qubit using dissipation via coupling to a lossy object. We look at the limiting factors in this approach to error correction, and how we address those by numerically optimizing the parametric coupling strength with the lossy object having an effective time-varying dissipation rate---we call this a pulse-reset cycle. We then translate this approach to more efficient state stabilization to an abstracted three-qubit flip code, and end by looking at the Very Small Logical Qubit (VSLQ). By using these techniques, we can further increase logical state lifetimes for different architectures. We show significant advantages in using a pulse-reset cycle over numerically optimized, fixed parameter spaces.

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