arXiv subjects

Debanjan Bhowmik

Publications and source records attributed to Debanjan Bhowmik.

15 recordsLinked to original sources

arXiv2026

Warm-Start Quantum Approximate Optimization Algorithm for QAM MIMO Data Detection

Data detection in large-scale multiple-input multiple-output (MIMO) systems with higher-order quadrature amplitude modulation (QAM) remains a challenging problem due to the exponential complexity of the classical maximum likelihood (ML) detector. This challenge is further amplified by Gray-coded modulation, which introduces nonlinear symbol-to-bit mappings and transforms the problem into a higher-order unconstrained binary optimization (HUBO) formulation. To address this problem, this paper presents a hybrid quantum-classical detection framework that leverages a warm-start linear-ramp Quantum Approximate Optimization Algorithm (WSLR-QAOA) for solving the resulting HUBO problem. A structured warm-start based on a low-rank semidefinite relaxation, solved via a block coordinate descent (BCD) method, provides an efficient and high-quality initialization, while a linear ramp parameterization guides the QAOA optimization. Simulation results show that the proposed framework outperforms classical methods in terms of symbol error rate (SER) and converges faster than standard QAOA, while achieving performance close to the optimal ML detector. Furthermore, the WSLR-QAOA algorithm is validated on actual IBM quantum hardware, where it achieves near-ML performance at low SNR and maintains competitive accuracy at higher SNR despite moderate degradation due to hardware noise. This demonstrates the practical potential of the HUBO-based WSLR-QAOA algorithm for large-scale MIMO data detection.

eess.SP↗

arXiv2026

Artificial Neural Network (ANN) -- Oscillatory Neural Network (ONN) Hybrid System Using Domain-Wall Synapse Devices and Nano-Constriction Spin Hall Nano Oscillators

A coupled spintronic oscillator array has been considered attractive for neuromorphic computing applications. Experimental reports have shown the nano-constriction geometry to be a relatively easier-to-fabricate platform for implementing such spin oscillators, but most prior reports on training and inference algorithms for neuromorphic computing using spin oscillators have been mostly restricted to the nano-pillar geometry. Also, those prior reports involve updating the natural frequency values of the oscillators and moving the synchronization regions on to the data clusters during the offline learning phase, which has associated challenges. In this context, we design and simulate a novel artificial neural network (ANN) - oscillator neural network (ONN) algorithm where in the offline learning phase, the weight parameters of the ANN are updated such that the data clusters are instead moved to the synchronization regions of spin Hall nano oscillators (SHNOs) in the nano-constriction geometry, as obtained through micromagnetic simulations. We further simulate the on-chip inference part of the ANN-ONN algorithm where the ANN is implemented on a crossbar array of domain-wall synapse devices, as simulated here through micromagnetics, and the ONN is implemented on nano-constriction SHNOs. We show successful data classification for both binary and multi-class classification tasks to demonstrate the generalizability of our proposed scheme.

physics.app-ph↗

arXiv2025

Symbol Detection in a MIMO Wireless Communication System Using a FeFET-coupled CMOS Ring Oscillator Array

Symbol decoding in multiple-input multiple-output (MIMO) wireless communication systems requires the deployment of fast, energy-efficient computing hardware deployable at the edge. The brute-force, exact maximum likelihood (ML) decoder, solved on conventional classical digital hardware, has exponential time complexity. Approximate classical solvers implemented on the same hardware have polynomial time complexity at the best. In this article, we design an alternative ring-oscillator-based coupled oscillator array to act as an oscillator Ising machine (OIM) and heuristically solve the ML-based MIMO detection problem. Complementary metal oxide semiconductor (CMOS) technology is used to design the ring oscillators, and ferroelectric field effect transistor (FeFET) technology is chosen as the coupling element (X) between the oscillators in this CMOS + X OIM design. For this purpose, we experimentally report high linear range of conductance variation (1 micro-S to 60 micro-S) in a FeFET device fabricated at 28 nm high-K/ metal gate (HKMG) CMOS technology node. We incorporate the conductance modulation characteristic in SPICE simulation of the ring oscillators connected in an all-to-all fashion through a crossbar array of these FeFET devices. We show that the above range of conductance variation of the FeFET device is suitable to obtain optimum OIM performance with no significant performance drop up to a MIMO size of 100 transmitting and 100 receiving antennas, thereby making FeFET a suitable device for this application. Our simulations and associated analysis using the Kuramoto model of oscillators also predict that this designed classical analog OIM, if implemented experimentally, will offer logarithmic scaling of computation time with MIMO size, thereby offering a huge improvement (in terms of computation speed) over aforementioned MIMO decoders run on conventional digital hardware.

physics.app-ph↗

arXiv2024

Vertically Integrated Dual-memtransistor Enabled Reconfigurable Heterosynaptic Sensorimotor Networks and In-memory Neuromorphic Computing

Neuromorphic in-memory computing requires area-efficient architecture for seamless and low latency parallel processing of large volumes of data. Here, we report a compact, vertically integrated/stratified field-effect transistor (VSFET) consisting of a 2D non-ferroelectric MoS$_2$ FET channel stacked on a 2D ferroelectric In$_2$Se$_3$ FET channel. Electrostatic coupling between the ferroelectric and non-ferroelectric semiconducting channels results in hysteretic transfer and output characteristics of both FETs. The gate-controlled MoS$_2$ memtransistor is shown to emulate homosynaptic plasticity behavior with low nonlinearity, low epoch, and high accuracy supervised (ANN - artificial neural network) and unsupervised (SNN - spiking neural network) on-chip learning. Further, simultaneous measurements of the MoS$_2$ and In$_2$Se$_3$ transistor synapses help realize complex heterosynaptic cooperation and competition behaviors. These are shown to mimic advanced sensorimotor neural network-controlled gill withdrawal reflex sensitization and habituation of a sea mollusk (Aplysia) with ultra-low power consumption. Finally, we show logic reconfigurability of the VSFET to realize Boolean gates thereby adding significant design flexibility for advanced computing technologies.

physics.app-ph↗

arXiv2023

Phase-Binarized Spintronic Oscillators for Combinatorial Optimization, and Comparison with Alternative Classical and Quantum Methods

Solving combinatorial optimization problems efficiently through emerging hardware by converting the problem to its equivalent Ising model and obtaining its ground state is known as Ising computing. Phase-binarized oscillators (PBO), modeled through the Kuramoto model, have been proposed for Ising computing, and various device technologies have been used to experimentally implement such PBOs. In this paper, we show that an array of four dipole-coupled uniform-mode spin Hall nano oscillators (SHNOs) can be used to implement such PBOs and solve the NP-Hard combinatorial problem MaxCut on 4-node complete weighted graphs. We model the spintronic oscillators through two techniques: an approximate model for coupled magnetization dynamics of spin oscillators, and Landau Lifshitz Gilbert Slonckzweski (LLGS) equation-based more accurate magnetization dynamics modeling of such oscillators. Next, we compare the performance of these room-temperature-operating spin oscillators, as well as generalized PBOs, with two other alternative methods that solve the same MaxCut problem: a classical approximation algorithm, known as Goemans-Williamson's (GW) algorithm, and a Noisy Intermediate Scale Quantum (NISQ) algorithm, known as Quantum Approximation Optimization Algorithm (QAOA). For four types of graphs, with graph size up to twenty nodes, we show that approximation ratio (AR) and success probability (SP) obtained for generalized PBOs (Kuramoto model), as well as spin oscillators, are comparable to that for GW and much higher than that of QAOA for almost all graph instances. Moreover, unlike GW, the time to solution (TTS) for generalized PBOs and spin oscillators does not grow with graph size for the instances we have explored. This can be a major advantage for PBOs in general and spin oscillators specifically for solving these types of problems, along with the accuracy of solutions they deliver.

physics.app-ph↗

arXiv2020

An Algorithm for Fast Supervised Learning in Variational Circuits through Simultaneous Processing of Multiple Samples

We propose a novel algorithm for fast training of variational classifiers by processing multiple samples parallelly. The algorithm can be adapted for any ansatz used in the variational circuit. The presented algorithm utilizes qRAM and other quantum circuits in the forward pass. Further, instead of the usual practice of computing the loss classically, we calculate the loss using a Swap-test circuit. The algorithm thus brings down the training cost of a variational classifier to O(logN)from the usual O(N)when training on a dataset of N samples. Although we discuss only binary classification in the paper, the algorithm can be easily generalized to multi-class classification.

quant-ph↗

arXiv2020

Supervised Learning Using a Dressed Quantum Network with "Super Compressed Encoding": Algorithm and Quantum-Hardware-Based Implementation

Implementation of variational Quantum Machine Learning (QML) algorithms on Noisy Intermediate-Scale Quantum (NISQ) devices is known to have issues related to the high number of qubits needed and the noise associated with multi-qubit gates. In this paper, we propose a variational QML algorithm using a dressed quantum network to address these issues. Using the "super compressed encoding" scheme that we follow here, the classical encoding layer in our dressed network drastically scales down the input-dimension, before feeding the input to the variational quantum circuit. Hence, the number of qubits needed in our quantum circuit goes down drastically. Also, unlike in most other existing QML algorithms, our quantum circuit consists only of single-qubit gates, making it robust against noise. These factors make our algorithm suitable for implementation on NISQ hardware. To support our argument, we implement our algorithm on real NISQ hardware and thereby show accurate classification using popular machine learning data-sets like Fisher's Iris, Wisconsin's Breast Cancer (WBC), and Abalone. Then, to provide an intuitive explanation for our algorithm's working, we demonstrate the clustering of quantum states, which correspond to the input-samples of different output-classes, on the Bloch sphere (using WBC and MNIST data-sets). This clustering happens as a result of the training process followed in our algorithm. Through this Bloch-sphere-based representation, we also show the distinct roles played (in training) by the adjustable parameters of the classical encoding layer and the adjustable parameters of the variational quantum circuit. These parameters are adjusted iteratively during training through loss-minimization.

quant-ph↗

arXiv2019

Comparing domain wall synapse with other Non Volatile Memory devices for on-chip learning in Analog Hardware Neural Network

Resistive Random Access Memory (RRAM) and Phase Change Memory (PCM) devices have been popularly used as synapses in crossbar array based analog Neural Network (NN) circuit to achieve more energy and time efficient data classification compared to conventional computers. Here we demonstrate the advantages of recently proposed spin orbit torque driven Domain Wall (DW) device as synapse compared to the RRAM and PCM devices with respect to on-chip learning (training in hardware) in such NN. Synaptic characteristic of DW synapse, obtained by us from micromagnetic modeling, turns out to be much more linear and symmetric (between positive and negative update) than that of RRAM and PCM synapse. This makes design of peripheral analog circuits for on-chip learning much easier in DW synapse based NN compared to that for RRAM and PCM synapses. We next incorporate the DW synapse as a Verilog-A model in the crossbar array based NN circuit we design on SPICE circuit simulator. Successful on-chip learning is demonstrated through SPICE simulations on the popular Fisher's Iris dataset. Time and energy required for learning turn out to be orders of magnitude lower for DW synapse based NN circuit compared to that for RRAM and PCM synapse based NN circuits.

physics.app-ph↗

arXiv2019

Supervised learning with a quantum classifier using a multi-level system

We propose a quantum classifier, which can classify data under the supervised learning scheme using a quantum feature space. The input feature vectors are encoded in a single qu$N$it (a $N$ level quantum system), as opposed to more commonly used entangled multi-qubit systems. For training we use the much used quantum variational algorithm -- a hybrid quantum-classical algorithm -- in which the forward part of the computation is performed on a quantum hardware whereas the feedback part is carried out on a classical computer. We introduce "single shot training" in our scheme, with all input samples belonging to the same class being used to train the classifier simultaneously. This significantly speeds up the training procedure and provides an advantage over classical machine learning classifiers. We demonstrate successful classification of popular benchmark datasets with our quantum classifier and compare its performance with respect to some classical machine learning classifiers. We also show that the number of training parameters in our classifier is significantly less than the classical classifiers.

quant-ph↗

arXiv2019

On-chip learning in a conventional silicon MOSFET based Analog Hardware Neural Network

On-chip learning in a crossbar array based analog hardware Neural Network (NN) has been shown to have major advantages in terms of speed and energy compared to training NN on a traditional computer. However analog hardware NN proposals and implementations thus far have mostly involved Non Volatile Memory (NVM) devices like Resistive Random Access Memory (RRAM), Phase Change Memory (PCM), spintronic devices or floating gate transistors as synapses. Fabricating systems based on RRAM, PCM or spintronic devices need in-house laboratory facilities and cannot be done through merchant foundries, unlike conventional silicon based CMOS chips. Floating gate transistors need large voltage pulses for weight update, making on-chip learning in such systems energy inefficient. This paper proposes and implements through SPICE simulations on-chip learning in analog hardware NN using only conventional silicon based MOSFETs (without any floating gate) as synapses since they are easy to fabricate. We first model the synaptic characteristic of our single transistor synapse using SPICE circuit simulator and benchmark it against experimentally obtained current-voltage characteristics of a transistor. Next we design a Fully Connected Neural Network (FCNN) crossbar array using such transistor synapses. We also design analog peripheral circuits for neuron and synaptic weight update calculation, needed for on-chip learning, again using conventional transistors. Simulating the entire system on SPICE simulator, we obtain high training and test accuracy on the standard Fisher's Iris dataset, widely used in machine learning. We also compare the speed and energy performance of our transistor based implementation of analog hardware NN with some previous implementations of NN with NVM devices and show comparable performance with respect to on-chip learning.

cs.NE↗

arXiv2018

On-chip learning for domain wall synapse based Fully Connected Neural Network

Spintronic devices are considered as promising candidates in implementing neuromorphic systems or hardware neural networks, which are expected to perform better than other existing computing systems for certain data classification and regression tasks. In this paper, we have designed a feedforward Fully Connected Neural Network (FCNN) with no hidden layer using spin orbit torque driven domain wall devices as synapses and transistor based analog circuits as neurons. A feedback circuit is also designed using transistors, which at every iteration computes the change in weights of the synapses needed to train the network using Stochastic Gradient Descent (SGD) method. Subsequently it sends write current pulses to the domain wall based synaptic devices which move the domain walls and updates the weights of the synapses. Through a combination of micromagnetic simulations, analog circuit simulations and numerically solving FCNN training equations, we demonstrate "on-chip" training of the designed FCNN on the MNIST database of handwritten digits in this paper. We report the training and test accuracies, energy consumed in the synaptic devices for the training and possible issues with hardware implementation of FCNN that can limit its test accuracy.

physics.app-ph↗

arXiv2015

Switching of Perpendicularly Polarized Nanomagnets with Spin Orbit Torque without an External Magnetic Field by Engineering a Tilted Anisotropy

Spin orbit torque (SOT) provides an efficient way of generating spin current that promises to significantly reduce the current required for switching nanomagnets. However, an in-plane current generated SOT cannot deterministically switch a perpendicularly polarized magnet due to symmetry reasons. On the other hand, perpendicularly polarized magnets are preferred over in-plane magnets for high-density data storage applications due to their significantly larger thermal stability in ultra-scaled dimensions. Here we show that it is possible switch a perpendicularly polarized magnet by SOT without needing an external magnetic field. This is accomplished by engineering an anisotropy in the magnets such that the magnetic easy axis slightly tilts away from the film-normal. Such a tilted anisotropy breaks the symmetry of the problem and makes it possible to switch the magnet deterministically. Using a simple Ta/CoFeB/MgO/Ta heterostructure, we demonstrate reversible switching of the magnetization by reversing the polarity of the applied current. This demonstration presents a new approach for controlling nanomagnets with spin orbit torque.

cond-mat.mtrl-sci↗

arXiv2014

Deterministic Domain Wall Motion Orthogonal To Current Flow Due To Spin Orbit Torque

Deterministic control of domain walls orthogonal to the direction of current flow is demonstrated by exploiting spin orbit torque in a perpendicularly polarized Ta/CoFeB/MgO multilayer in presence of an in-plane magnetic field. Notably, such orthogonal motion with respect to current flow is not possible from traditional spin transfer torque driven domain wall propagation even in presence of an external magnetic field. Reversing the polarity of either the current flow or the in-plane field is found to reverse the direction of the domain wall motion. From these measurements, which are unaffected by any conventional spin transfer torque by symmetry, we estimate the spin orbit torque efficiency of Ta to be 0.08.

cond-mat.mtrl-sci↗

arXiv2011

Experimental Evidence of Ferroelectric Negative Capacitance in Nanoscale Heterostructures

We report a proof-of-concept demonstration of negative capacitance effect in a nanoscale ferroelectric-dielectric heterostructure. In a bilayer of ferroelectric, Pb(Zr0.2Ti0.8)O3 and dielectric, SrTiO3, the composite capacitance was observed to be larger than the constituent SrTiO3 capacitance, indicating an effective negative capacitance of the constituent Pb(Zr0.2Ti0.8)O3 layer. Temperature is shown to be an effective tuning parameter for the ferroelectric negative capacitance and the degree of capacitance enhancement in the heterostructure. Landau's mean field theory based calculations show qualitative agreement with observed effects. This work underpins the possibility that by replacing gate oxides by ferroelectrics in MOSFETs, the sub threshold slope can be lowered below the classical limit (60 mV/decade).

cond-mat.mes-hall↗

arXiv2010

A reconfigurable spintronic device for quantum and classical logic

Quantum superposition and entanglement of physical states can be harnessed to solve some problems which are intractable on a classical computer implementing binary logic. Several algorithms have been proposed to utilize the quantum nature of physical states and solve important problems. For example, Shor's quantum algorithm is extremely important in the field of cryptography since it factors large numbers exponentially faster than any known classical algorithm. Another celebrated example is the Grovers quantum algorithm. These algorithms can only be implemented on a quantum computer which operates on quantum bits (qubits). Rudimentary implementations of quantum processor have already been achieved through linear optical components, ion traps, NMR etc. However demonstration of a solid state quantum processor had been elusive till DiCarlo et al demonstrated two qubit algorithms in superconducting quantum processor. Though this has been a significant step, scalable semiconductor based room temperature quantum computing is yet to be found. Such a technology could benefit from the vast experience of the semiconductor industry. Hence, here we present a reconfigurable semiconductor quantum logic device (SQuaLD) which operates on the position and spin degree of freedom of the electrons in the device. Based on a few recent experiments, we believe SQuaLD is experimentally feasible. Moreover, using a well known quantum simulation method, we show that quantum algorithms (such as Deutsch Jozsa, Grover search) as well as universal classical logic operations (such as NAND gate) can be implemented in SQuaLD. Thus, we argue that SQuaLD is a strong candidate for the future quantum logic processor since it also satisfies the DiVincenzo criteria for quantum logic application as well as the five essential characteristics for classical logic applications.

quant-ph↗