arXiv subjects

Debasri Saha

Publications and source records attributed to Debasri Saha.

14 recordsLinked to original sources

arXiv2025

AFarePart: Accuracy-aware Fault-resilient Partitioner for DNN Edge Accelerators

Deep Neural Networks (DNNs) are increasingly deployed across distributed and resource-constrained platforms, such as System-on-Chip (SoC) accelerators and edge-cloud systems. DNNs are often partitioned and executed across heterogeneous processing units to optimize latency and energy. However, the reliability of these partitioned models under hardware faults and communication errors remains a critical yet underexplored topic, especially in safety-critical applications. In this paper, we propose an accuracy-aware, fault-resilient DNN partitioning framework targeting multi-objective optimization using NSGA-II, where accuracy degradation under fault conditions is introduced as a core metric alongside energy and latency. Our framework performs runtime fault injection during optimization and utilizes a feedback loop to prioritize fault-tolerant partitioning. We evaluate our approach on benchmark CNNs including AlexNet, SqueezeNet and ResNet18 on hardware accelerators, and demonstrate up to 27.7% improvement in fault tolerance with minimal increase in performance overhead. Our results highlight the importance of incorporating resilience into DNN partitioning, and thereby paving the way for robust AI inference in error-prone environments.

cs.PF↗

arXiv2024

Scalable Test Generation to Trigger Rare Targets in High-Level Synthesizable IPs for Cloud FPGAs

High-Level Synthesis (HLS) has transformed the development of complex Hardware IPs (HWIP) by offering abstraction and configurability through languages like SystemC/C++, particularly for Field Programmable Gate Array (FPGA) accelerators in high-performance and cloud computing contexts. These IPs can be synthesized for different FPGA boards in cloud, offering compact area requirements and enhanced flexibility. HLS enables designs to execute directly on ARM processors within modern FPGAs without the need for Register Transfer Level (RTL) synthesis, thereby conserving FPGA resources. While HLS offers flexibility and efficiency, it also introduces potential vulnerabilities such as the presence of hidden circuitry, including the possibility of hosting hardware trojans within designs. In cloud environments, these vulnerabilities pose significant security concerns such as leakage of sensitive data, IP functionality disruption and hardware damage, necessitating the development of robust testing frameworks. This research presents an advanced testing approach for HLS-developed cloud IPs, specifically targeting hidden malicious functionalities that may exist in rare conditions within the design. The proposed method leverages selective instrumentation, combining greybox fuzzing and concolic execution techniques to enhance test generation capabilities. Evaluation conducted on various HLS benchmarks, possessing characteristics of FPGA-based cloud IPs with embedded cloud related threats, demonstrates the effectiveness of our framework in detecting trojans and rare scenarios, showcasing improvements in coverage, time efficiency, memory usage, and testing costs compared to existing methods.

cs.CR↗

arXiv2023

AgEncID: Aggregate Encryption Individual Decryption of Key for FPGA Bitstream IP Cores in Cloud

Cloud computing platforms are progressively adopting Field Programmable Gate Arrays to deploy specialized hardware accelerators for specific computational tasks. However, the security of FPGA-based bitstream for Intellectual Property, IP cores from unauthorized interception in cloud environments remains a prominent concern. Existing methodologies for protection of such bitstreams possess several limitations, such as requiring a large number of keys, tying bitstreams to specific FPGAs, and relying on trusted third parties. This paper proposes Aggregate Encryption and Individual Decryption, a cryptosystem based on key aggregation to enhance the security of FPGA-based bitstream for IP cores and to address the pitfalls of previous related works. In our proposed scheme, IP providers can encrypt their bitstreams with a single key for a set S of FPGA boards, with which the bitstreams can directly be decrypted on any of the FPGA boards in S. Aggregate encryption of the key is performed in a way which ensures that the key can solely be obtained onboard through individual decryption employing the board's private key, thus facilitating secure key provisioning. The proposed cryptosystem is evaluated mainly on Zynq FPGAs. The outcomes demonstrate that our cryptosystem not only outperforms existing techniques with respect to resource, time and energy significantly but also upholds robust security assurances.

cs.CR↗

arXiv2022

GreyConE: Greybox fuzzing+Concolic execution guided test generation for high level design

Exhaustive testing of high-level designs pose an arduous challenge due to complex branching conditions, loop structures and inherent concurrency of hardware designs. Test engineers aim to generate quality test-cases satisfying various code coverage metrics to ensure minimal presence of bugs in a design. Prior works in testing SystemC designs are time inefficient which obstruct achieving the desired coverage in shorter time-span. We interleave greybox fuzzing and concolic execution in a systematic manner and generate quality test-cases accelerating test coverage metrics. Our results outperform state-of-the-art methods in terms of number of test cases and branch-coverage for some of the benchmarks, and runtime for most of them.

cs.SE↗

arXiv2022

Discrete-time Quantum Walks in Qudit Systems

Quantum walks contribute significantly to developing quantum algorithms and quantum simulations. Here, we introduce a first of its kind one-dimensional quantum walk in the $d$-dimensional quantum domain, where $d>2$, and show its equivalence for circuit realization in an arbitrary finite-dimensional quantum logic for utilizing the advantage of larger state space, which helps to reduce the run-time of the quantum walks as compared to the conventional binary quantum systems. We provide efficient quantum circuits for the implementation of discrete-time quantum walks (DTQW) in one-dimensional position space in any finite-dimensional quantum system when the dimension is odd using an appropriate logical mapping of the position space on which a walker evolves onto the multi-qudit states. With example circuits for various qudit state spaces, we also explore scalability in terms of $n$-qudit $d$-ary quantum systems. Further, the extension of one-dimensional DTQW to $d$-dimensional DTQW using $2d$-dimensional coin space on $d$-dimensional lattice has been studied, where $d>=2$. Thereafter, the circuit design for the implementation of scalable $d$-dimensional DTQW in $d$-ary quantum systems has been portrayed. Lastly, we exhibit the circuit design for the implementation of DTQW using different coins on various search spaces.

quant-ph↗

arXiv2022

Asymptotically Improved Circuit for $d$-ary Grover's Algorithm with Advanced Decomposition of $n$-qudit Toffoli Gate

The progress in building quantum computers to execute quantum algorithms has recently been remarkable. Grover's search algorithm in a binary quantum system provides considerable speed-up over classical paradigm. Further, Grover's algorithm can be extended to a $d$-ary (qudit) quantum system for utilizing the advantage of larger state space, which helps to reduce the run-time of the algorithm as compared to the traditional binary quantum systems. In a qudit quantum system, an $n$-qudit Toffoli gate plays a significant role in the accurate implementation of Grover's algorithm. In this article, a generalized $n$-qudit Toffoli gate has been realized using higher dimensional qudits to attain a logarithmic depth decomposition without ancilla qudit. The circuit for Grover's algorithm has then been designed for any $d$-ary quantum system, where $d \ge 2$, with the proposed $n$-qudit Toffoli gate to obtain optimized depth compared to earlier approaches. The technique for decomposing an $n$-qudit Toffoli gate requires access to two immediately higher energy levels, making the design susceptible to errors. Nevertheless, we show that the percentage decrease in the probability of error is significant as we have reduced both gate count and circuit depth as compared to that in state-of-the-art works.

quant-ph↗

arXiv2021

FuCE: Fuzzing+Concolic Execution guided Trojan Detection in Synthesizable Hardware Designs

High-level synthesis (HLS) is the next emerging trend for designing complex customized architectures for applications such as Machine Learning, Video Processing. It provides a higher level of abstraction and freedom to hardware engineers to perform hardware software co-design. However, it opens up a new gateway to attackers to insert hardware trojans. Such trojans are semantically more meaningful and stealthy, compared to gate-level trojans and therefore are hard-to-detect using state-of-the-art gate-level trojan detection techniques. Although recent works have proposed detection mechanisms to uncover such stealthy trojans in high-level synthesis (HLS) designs, these techniques are either specially curated for existing trojan benchmarks or may run into scalability issues for large designs. In this work, we leverage the power of greybox fuzzing combined with concolic execution to explore deeper segments of design and uncover stealthy trojans. Experimental results show that our proposed framework is able to automatically detect trojans faster with fewer test cases, while attaining notable branch coverage, without any manual pre-processing analysis.

cs.CR↗

arXiv2021

Circuit Design for $k$-coloring Problem and Its Implementation on Near-term Quantum Devices

Nowadays in Quantum Computing, the implementation of quantum algorithm has created a stir since Noisy Intermediate-Scale Quantum (NISQ) devices are out in the market. Researchers are mostly interested in solving NP-complete problems with the help of quantum algorithms for its speed-up. As per the work on computational complexity by Karp \cite{karp}, if any of the NP-complete problem can be solved then any other NP-complete problem can be reduced to that problem in polynomial time. In this Paper, $k$-coloring problem (NP-complete problem) has been considered to solve using Grover's search. A comparator-based approach has been used to implement $k$-coloring problem which enables the reduction of the qubit cost compared to the state-of-the-art. An end-to-end automated framework has been proposed to implement the $k$-coloring problem for any unweighted and undirected graph on any available Noisy Intermediate-Scale Quantum (NISQ) devices, which helps in generalizing our approach.

cs.ET↗

arXiv2021

Circuit Design for Clique Problem and Its Implementation on Quantum Computer

Finding cliques in a graph has several applications for its pattern matching ability. $k$-clique problem, a special case of clique problem, determines whether an arbitrary graph contains a clique of size $k$, has already been addressed in quantum domain. A variant of $k$-clique problem that lists all cliques of size $k$, has also popular modern-day applications. Albeit, the implementation of such variant of $k$-clique problem in quantum setting still remains untouched. In this paper, apart from theoretical solution of such $k$-clique problem, practical quantum gate-based implementation has been addressed using Grover's algorithm. This approach is further extended to design circuit for the maximum clique problem in classical-quantum hybrid architecture. The algorithm automatically generates the circuit for any given undirected and unweighted graph and any given $k$, which makes our approach generalized in nature. The proposed approach of solving $k$-clique problem has exhibited a reduction of qubit cost and circuit depth as compared to the state-of-the-art approach, for a small $k$ with respect to a large graph. A framework that can map the automated generated circuit for clique problem to quantum devices is also proposed. An analysis of the experimental results is demonstrated using IBM's Qiskit.

cs.DS↗

arXiv2021

Faster Search of Clustered Marked States with Lackadaisical Quantum Walks

The nature of discrete-time quantum walk in the presence of multiple marked states has been studied by Nahimovs and Rivosh. They introduced an exceptional configuration of clustered marked states $i.e.,$ if the marked states are arranged in a $\sqrt{k} \times \sqrt{k}$ cluster within a $\sqrt{N} \times \sqrt{N}$ grid, where $k=n^{2}$ and $n$ an odd integer. They showed that finding a single marked state among the multiple ones using quantum walk with AKR (Ambainis, Kempe and Rivosh) coin requires $Ω(\sqrt{N} - \sqrt{k})$ time. Furthermore, Nahimov and Rivosh also showed that the Grover's coin can find the same configuration of marked state both faster and with higher probability compared to that with the AKR coin. In this article, we show that using lackadaisical quantum walk, a variant of a three-state discrete-time quantum walk on a line, the success probability of finding all the clustered marked states of this exceptional configuration is nearly 1 with smaller run-time. We also show that the weights of the self-loop suggested for multiple marked states in the state-of-the-art works are not optimal for this exceptional configuration of clustered mark states. We propose a range of weights of the self-loop from which only one can give the desired result for this configuration.

quant-ph↗

arXiv2021

Moving Quantum States without SWAP via Intermediate Higher Dimensional Qudits

Quantum algorithms can be realized in the form of a quantum circuit. To map quantum circuit for specific quantum algorithm to quantum hardware, qubit mapping is an imperative technique based on the qubit topology. Due to the neighbourhood constraint of qubit topology, the implementation of quantum algorithm rightly, is essential for moving information around in a quantum computer. Swapping of qubits using SWAP gate moves the quantum state between two qubits and solves the neighbourhood constraint of qubit topology. Though, one needs to decompose the SWAP gate into three CNOT gates to implement SWAP gate efficiently, but unwillingly quantum cost with respect to gate count and depth increases. In this paper, a new formalism of moving quantum states without using SWAP operation is introduced for the first time to the best of our knowledge. Moving quantum states through qubits have been attained with the adoption of temporary intermediate qudit states. This introduction of intermediate qudit states has exhibited a three times reduction in quantum cost with respect to gate count and approximately two times reduction in respect to circuit depth compared to the state-of-the-art approach of SWAP gate insertion. Further, the proposed approach is generalized to any dimensional quantum system.

quant-ph↗

arXiv2021

Circuit Design for $k$-coloring Problem and Its Implementation in Any Dimensional Quantum System

With the evolution of quantum computing, researchers now-a-days tend to incline to find solutions to NP-complete problems by using quantum algorithms in order to gain asymptotic advantage. In this paper, we solve $k$-coloring problem (NP-complete problem) using Grover's algorithm in any dimensional quantum system or any $d$-ary quantum system for the first time to the best of our knowledge, where $d \ge 2$. A newly proposed comparator-based approach helps to generalize the implementation of the $k$-coloring problem in any dimensional quantum system. Till date, $k$-coloring problem has been implemented only in binary and ternary quantum system, hence, we abide to $d=2$ or $d=3$, that is for binary and ternary quantum system for comparing our proposed work with the state-of-the-art techniques. This proposed approach makes the reduction of the qubit cost possible, compared to the state-of-the-art binary quantum systems. Further, with the help of newly proposed ternary comparator, a substantial reduction in quantum gate count for the ternary oracle circuit of the $k$-coloring problem than the previous approaches has been obtained. An end-to-end automated framework has been put forward for implementing the $k$-coloring problem for any undirected and unweighted graph on any available Near-term quantum devices or Noisy Intermediate-Scale Quantum (NISQ) devices or multi-valued quantum simulator, which helps in generalizing our approach.

cs.ET↗

arXiv2020

One-Dimensional Lazy Quantum walk in Ternary System

Quantum walks play an important role for developing quantum algorithms and quantum simulations. Here we present one dimensional three-state quantum walk(lazy quantum walk) and show its equivalence for circuit realization in ternary quantum logic for the first of its kind. Using an appropriate logical mapping of the position space on which a walker evolves onto the multi-qutrit states, we present efficient quantum circuits considering the nearest neighbour position space for the implementation of lazy quantum walks in one-dimensional position space in ternary quantum system. We also address scalability in terms of $n$-qutrit ternary system with example circuits for a three qutrit state space.

quant-ph↗

arXiv2018

Search of clustered marked states with lackadaisical quantum walks

Nature of quantum walk in presence of multiple marked state has been studied by Nahimovs and Rivosh \cite{10.1007/978-3-662-49192-8_31}. They have shown that if the marked states are arranged in a $\sqrt{k} \times \sqrt{k}$ cluster in a $\sqrt{N} \times \sqrt{N}$ grid, then to find a single marked state among the multiple ones, quantum walk requires $Ω(\sqrt{N} - \sqrt{k})$ time. In this paper, we show that using lackadaisical quantum walk with the weight of the self-loop as $\frac{4}{N(k + \lfloor{\frac{\sqrt{k}}{2}}\rfloor)}$, where $k$ is odd, the probability of finding a marked state increases by $\sim 0.2$. Furthermore, we show that instead of applying the quantum walk $\mathcal{O}(k)$ times to find all the marked states, classical search in the vicinity of the marked state found after the first implementation of the quantum walk can find all the marked states in $\mathcal{O}(\sqrt{k})$ time on average.

quant-ph↗