arXiv subjects

Dhirpal Shah

Publications and source records attributed to Dhirpal Shah.

4 recordsLinked to original sources

arXiv2026

Noisy Quantum Simulation Using Tracking, Uncomputation and Sampling

Quantum computers have rapidly improved in scale and fidelity, yet access to large systems remains limited for most researchers. This makes accurate and scalable noisy quantum simulation essential. While density matrix simulation provides the most faithful representation of noisy quantum systems, its exponential memory overhead severely limits scalability. Consequently, noisy simulations are commonly performed by: (a) sampling multiple circuit instances with fixed noise realizations from stochastic noise channels, and (b) executing simulations of these sampled circuits and averaging the results. However, this introduces significant computational overhead due to the large number of circuit evaluations required. Existing approaches reduce this overhead by caching intermediate states for reuse, but such methods become impractical when simulations are both compute and memory constrained. To address this challenge, we propose TUSQ - Tracking, Uncomputation, and Sampling for Noisy Quantum Simulation. TUSQ consists of two components: the Error Characterization Module (ECM) and Depth-First Tree Traversal (DFTT). ECM reduces redundant simulation by identifying equivalent error configurations through Error Tallying and Error Commutation, followed by importance sampling during pruning to reduce the number of circuit instances requiring simulation. DFTT then exploits structural similarity across the remaining circuits by organizing them into a tree and traversing it using compute/uncompute operations to efficiently reuse intermediate computation without additional memory overhead. We evaluate TUSQ across 198 benchmarks with 1 million shots each. TUSQ achieves average(maximum) speedups of 59.06x(7878.03x) over Qiskit and 13.38x(439.38x) over CUDA-Q. Compared to TQSim in compute and memory constrained settings, TUSQ achieves average and maximum speedups of 39.32x and 3134.31x, respectively.

quant-ph↗

arXiv2025

Toward Quantum-Enabled Biomarker Discovery: An Outlook from Q4Bio

We present a case study and forward-looking perspective on co-design for hybrid quantum-classical algorithms, centered on the goal of empirical quantum advantage (EQA), which we define as a measurable performance gain using quantum hardware over state-of-the-art classical methods on the same task. Because classical algorithms continue to improve, the EQA crossover point is a moving target; nevertheless, we argue that a persistent advantage is possible for our application class even if the crossover point shifts. Specifically, our team examines the task of biomarker discovery in precision oncology. We push the limitations of the best classical algorithms, improving them as best as we can, and then augment them with a quantum subroutine for the task where we are most likely to see performance gains. We discuss the implementation of a quantum subroutine for feature selection on current devices, where hardware constraints necessitate further co-design between algorithm and physical device capabilities. Looking ahead, we perform resource analysis to explore a plausible EQA region on near/intermediate-term hardware, considering the impacts of advances in classical and quantum computing on this regime. Finally, we outline potential clinical impact and broader applications of this hybrid pipeline beyond oncology.

quant-ph↗

arXiv2024

Circuit decompositions and scheduling for neutral atom devices with limited local addressability

Despite major ongoing advancements in neutral atom hardware technology, there remains limited work in systems-level software tailored to overcoming the challenges of neutral atom quantum computers. In particular, most current neutral atom architectures do not natively support local addressing of single-qubit rotations about an axis in the xy-plane of the Bloch sphere. Instead, these are executed via global beams applied simultaneously to all qubits. While previous neutral atom experimental work has used straightforward synthesis methods to convert short sequences of operations into this native gate set, these methods cannot be incorporated into a systems-level framework nor applied to entire circuits without imposing impractical amounts of serialization. Without sufficient compiler optimizations, decompositions involving global gates will significantly increase circuit depth, gate count, and accumulation of errors. No prior compiler work has addressed this, and adapting existing compilers to solve this problem is nontrivial. In this paper, we present an optimized compiler pipeline that translates an input circuit from an arbitrary gate set into a realistic neutral atom native gate set containing global gates. We focus on decomposition and scheduling passes that minimize the final circuit's global gate count and total global rotation amount. As we show, these costs contribute the most to the circuit's duration and overall error, relative to costs incurred by other gate types. Compared to the unoptimized version of our compiler pipeline, minimizing global gate costs gives up to 4.77x speedup in circuit duration. Compared to the closest prior existing work, we achieve up to 53.8x speedup. For large circuits, we observe a few orders of magnitude improvement in circuit fidelities.

quant-ph↗

arXiv2023

YFlows: Systematic Dataflow Exploration and Code Generation for Efficient Neural Network Inference using SIMD Architectures on CPUs

We address the challenges associated with deploying neural networks on CPUs, with a particular focus on minimizing inference time while maintaining accuracy. Our novel approach is to use the dataflow (i.e., computation order) of a neural network to explore data reuse opportunities using heuristic-guided analysis and a code generation framework, which enables exploration of various Single Instruction, Multiple Data (SIMD) implementations to achieve optimized neural network execution. Our results demonstrate that the dataflow that keeps outputs in SIMD registers while also maximizing both input and weight reuse consistently yields the best performance for a wide variety of inference workloads, achieving up to 3x speedup for 8-bit neural networks, and up to 4.8x speedup for binary neural networks, respectively, over the optimized implementations of neural networks today.

cs.AR↗