arXiv subjects

Diman Zad Tootaghaj

Publications and source records attributed to Diman Zad Tootaghaj.

4 recordsLinked to original sources

arXiv2018

CARMA: Contention-aware Auction-based Resource Management in Architecture

As the number of resources on chip multiprocessors (CMPs) increases, the complexity of how to best allocate these resources increases drastically. Because the higher number of applications makes the interaction and impacts of various memory levels more complex. Also, the selection of the objective function to define what \enquote{best} means for all applications is challenging. Memory-level parallelism (MLP) aware replacement algorithms in CMPs try to maximize the overall system performance or equalize each application's performance degradation due to sharing. However, depending on the selected \enquote{performance} metric, these algorithms are not efficiently implemented, because these centralized approaches mostly need some further information regarding about applications' need. In this paper, we propose a contention-aware game-theoretic resource management approach (CARMA) using market auction mechanism to find an optimal strategy for each application in a resource competition game. The applications learn through repeated interactions to choose their action on choosing the shared resources. Specifically, we consider two cases: (i) cache competition game, and (ii) main processor and co-processor congestion game. We enforce costs for each resource and derive bidding strategy. Accurate evaluation of the proposed approach show that our distributed allocation is scalable and outperforms the static and traditional approaches.

cs.DC↗

arXiv2017

High Five: Improving Gesture Recognition by Embracing Uncertainty

Sensors on mobile devices---accelerometers, gyroscopes, pressure meters, and GPS---invite new applications in gesture recognition, gaming, and fitness tracking. However, programming them remains challenging because human gestures captured by sensors are noisy. This paper illustrates that noisy gestures degrade training and classification accuracy for gesture recognition in state-of-the-art deterministic Hidden Markov Models (HMM). We introduce a new statistical quantization approach that mitigates these problems by (1) during training, producing gesture-specific codebooks, HMMs, and error models for gesture sequences; and (2) during classification, exploiting the error model to explore multiple feasible HMM state sequences. We implement classification in Uncertain , a probabilistic programming system that encapsulates HMMs and error models and then automates sampling and inference in the runtime. Uncertain developers directly express a choice of application-specific trade-off between recall and precision at gesture recognition time, rather than at training time. We demonstrate benefits in configurability, precision, recall, and recognition on two data sets with 25 gestures from 28 people and 4200 total gestures. Incorporating gesture error more accurately in modeling improves the average recognition rate of 20 gestures from 34\% in prior work to 62\%. Incorporating the error model during classification further improves the average gesture recognition rate to 71\%. As far as we are aware, no prior work shows how to generate an HMM error model during training and use it to improve classification rates.

cs.CV↗

arXiv2016

Optimal Placement of Cores, Caches and Memory Controllers in Network On-Chip

Parallel programming is emerging fast and intensive applications need more resources, so there is a huge demand for on-chip multiprocessors. Accessing L1 caches beside the cores are the fastest after registers but the size of private caches cannot increase because of design, cost and technology limits. Then split I-cache and D-cache are used with shared LLC (last level cache). For a unified shared LLC, bus interface is not scalable, and it seems that distributed shared LLC (DSLLC) is a better choice. Most of papers assume a distributed shared LLC beside each core in on-chip network. Many works assume that DSLLCs are placed in all cores; however, we will show that this design ignores the effect of traffic congestion in on-chip network. In fact, our work focuses on optimal placement of cores, DSLLCs and even memory controllers to minimize the expected latency based on traffic load in a mesh on-chip network with fixed number of cores and total cache capacity. We try to do some analytical modeling deriving intended cost function and then optimize the mean delay of the on-chip network communication. This work is supposed to be verified using some traffic patterns that are run on CSIM simulator.

cs.PF↗

arXiv2016

Towards Stochastically Optimizing Data Computing Flows

With rapid growth in the amount of unstructured data produced by memory-intensive applications, large scale data analytics has recently attracted increasing interest. Processing, managing and analyzing this huge amount of data poses several challenges in cloud and data center computing domain. Especially, conventional frameworks for distributed data analytics are based on the assumption of homogeneity and non-stochastic distribution of different data-processing nodes. The paper argues the fundamental limiting factors for scaling big data computation. It is shown that as the number of series and parallel computing servers increase, the tail (mean and variance) of the job execution time increase. We will first propose a model to predict the response time of highly distributed processing tasks and then propose a new practical computational algorithm to optimize the response time.

cs.DC↗