arXiv subjects

Dimitris Antoniadis

Publications and source records attributed to Dimitris Antoniadis.

3 recordsLinked to original sources

arXiv2026

Neural implants and human safety: single-fault detection for DC-coupled recording front ends

DC-coupled analogue front ends (AFEs) for neural implants provide a low-area solution. However, removing the coupling capacitor eliminates the intrinsic barrier that protects cortical tissue: a single-fault event, such as gate-oxide breakdown of a low-noise amplifier (LNA) input transistor, can open a direct DC path from the supply rail into the brain. On the stimulation side this hazard is well understood, and single-fault tolerance is enforced by a series DC-blocking capacitor; on the recording side, DC-coupled front ends discard the equivalent safeguard, yet their protection has gone almost unexamined. This paper presents a single-fault detection mechanism that monitors the LNA for the DC imbalance produced by such a failure and disables the amplifier before the resulting fault current can irreversibly damage tissue. The imbalance is encoded in the duty cycle of a current-starved relaxation oscillator and read out as a time-to-digital measurement. Designed in 65 nm, the mechanism resolves a worst-case fault of 6.4 nA across all corners within 0.81 ms - compliant with the ISO~14708-3 limit for an 8533 um2 electrode - opening a broader discussion of safety in DC-coupled recording.

eess.SP↗

arXiv2025

A mixed-signal analogue front-end for brain-implantable neural interfaces using a digital fixed-point IIR filter and bulk offset cancellation

Advances in miniaturised implantable neural electronics have paved the way for therapeutic brain-computer interfaces with clinical potential for movement disorders, epilepsy, and broader neurological applications. This paper presents a mixed-signal analogue front end (AFE) designed to record simultaneously both extracellular action potentials (EAPs) and local field potentials (LFPs). The feedforward path integrates a low-noise amplifier (LNA) and a successive-approximation-register (SAR) analogue-to-digital converter (ADC), while the feedback path employs a fixed-point infinite-impulse-response (IIR) Chebyshev Type II low-pass filter to suppress sub-mHz components via bulk-voltage control of the LNA input differential pair using two R-2R pseudo-resistor digital-to-analogue converters (DACs). The proposed AFE employs a low-power (LP) mode and an offset-cancellation high-performance (HP) mode. The proposed AFE achieves 40.55 dB gain and supports neural recording from 0.1 Hz to 5.705 / 9.66 kHz (LP / HP), with typical input-referred noise of 3.9 / 6.615 uVrms in the LFP band and 11.42 / 11.11 uVrms in the EAP band (LP / HP). Its typical power per channel is 5.44 uW (LP) and 11.35 uW (HP), while it occupies 0.198 mm2.

eess.SP↗

arXiv2021

An Open-Source RRAM Compiler

Memory compilers are necessary tools to boost the design procedure of digital circuits. However, only a few are available to academia. Resistive Random Access Memory (RRAM) is characterised by high density, high speed, non volatility and is a potential candidate of future digital memories. To the best of the authors' knowledge, this paper presents the first open source RRAM compiler for automatic memory generation including its peripheral circuits, verification and timing characterisation. The RRAM compiler is written with Cadence SKILL programming language and is integrated in Cadence environment. The layout verification procedure takes place in Siemens Mentor Calibre tool. The technology used by the compiler is TSMC 180nm. This paper analyses the novel results of a plethora of M x N RRAMs generated by the compiler, up to M = 128, N = 64 and word size B = 16 bits, for clock frequency equal to 12.5 MHz. Finally, the compiler achieves density of up to 0.024 Mb/mm2.

cs.ET↗