Beyond the Parasitic Limit: A Nanoprobing Framework for De-embedding Intrinsic Ferroelectric Properties at the Deep Sub-Micrometer Scale
The continued scaling of ferroelectric devices is critical for next-generation computing architectures, yet it is fundamentally challenged by a metrological bottleneck: at the deep sub-micrometer scale, intrinsic material properties are heavily masked by extrinsic parasitic impedances and geometric fringing fields. Here, we introduce a quantitative, in-situ nanoprobing framework capable of resolving the true electrical response of ferroelectric capacitors down to 165 nm in diameter without the need for lithographic bond pads. Using 20 nm thick AlScN as a model system, we establish a non-linear 'Screened Power Law' model to decouple attofarad-level device capacitances from massive near-field probe interactions. Furthermore, we demonstrate that the apparent degradation of dielectric loss at the nanoscale is a geometric dilution artifact, which we overcome through a conductance scaling analysis. Finally, we apply this framework to large-signal characterization, utilizing leakage-compensation and noise filtering protocols to extract pristine intrinsic hysteresis (C-V and J-E) loops in the discrete few-grain limit. These findings provide a universal analytical toolkit required to overcome the measurement limits of deep-submicron ferroelectrics.