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Edouard Deschaseaux

Publications and source records attributed to Edouard Deschaseaux.

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Sub-kelvin thermal conductivity of substrates and on-chip routing in quantum integrated systems

The development of large-scale quantum systems increasingly relies on the close integration of heterogeneous components such as qubits, control electronics, and readout circuits, making thermal management at cryogenic temperatures a central challenge in such architectures. In this work, we present an experimental thermal study of two building blocks of such systems: the substrate and the on-chip routing. We first investigate the sub-kelvin thermal conductivity of four substrate materials: high-resistivity silicon, low-resistivity silicon, borosilicate, and sapphire. We report that high-resistivity silicon exhibits the highest thermal conductivity among the substrates studied ($5\cdot10^{-2}$~W/m$\cdot$K at 300~mK), while low-resistivity silicon, borosilicate, and sapphire show lower values ($8\cdot10^{-4}$~W/m$\cdot$K, 2$\cdot10^{-3}$~W/m$\cdot$K, and 2$\cdot10^{-3}$~W/m$\cdot$K at 300~mK, respectively). Ballistic conductance evaluation using a finite-element non-equilibrium Green's function approach further allows us to extract the phonon mean free path in each substrate and gives insights into the involved scattering mechanisms. Additionally, we employ a dedicated test vehicle to evaluate the impact of on-chip routing on the thermal conductance of the system. Our measurements with superconducting Nb routing lines reveal that the routing increases the in-plane thermal conductance of the system, but the substrate remains the dominant heat path. These results highlight the critical role of the substrate choice within quantum systems and underscore the importance of function partitioning through 3D integration approaches for more efficient thermal management in quantum architectures.

cond-mat.mes-hall

Superconducting routing platform for large-scale integration of quantum technologies

To reach large-scale quantum computing, three-dimensional integration of scalable qubit arrays and their control electronics in multi-chip assemblies is promising. Within these assemblies, the use of superconducting interconnections, as routing layers, offers interesting perspective in terms of (1) thermal management to protect the qubits from control electronics self-heating, (2) passive device performance with significant increase of quality factors and (3) density rise of low and high frequency signals thanks to minimal dispersion. We report on the fabrication, using 200 mm silicon wafer technologies, of a multi-layer routing platform designed for the hybridization of spin qubit and control electronics chips. A routing level couples the qubits and the control circuits through one layer of Al0.995Cu0.005 and superconducting layers of TiN, Nb or NbN, connected between them by W-based vias. Wafer-level parametric tests at 300 K validate the yield of these technologies and low temperature electrical measurements in cryostat are used to extract the superconducting properties of the routing layers. Preliminary low temperature radio-frequency characterizations of superconducting passive elements, embedded in these routing levels, are presented.

cond-mat.mes-hall