arXiv subjects

Edwin Tham

Publications and source records attributed to Edwin Tham.

11 recordsLinked to original sources

arXiv2026

Breakeven demonstration of quantum low-density parity-check codes

High-rate quantum low-density parity-check (qLDPC) codes are a leading candidate for fault-tolerant quantum computing. They feature higher encoding rates than planar alternatives such as the surface code, but their implementation often entails significant hardware hurdles like the need for long-range couplers. We leverage the flexibility of a trapped-ion quantum computer to demonstrate nine quantum error-correcting codes with starkly different qubit connectivity requirements on a single device without any hardware reconfiguration. These experiments span three families of quantum error-correcting codes: qLDPC codes, topological codes, and concatenated codes. With a qLDPC code encoding 4 logical qubits into 18 physical qubits, we achieve a logical error rate up to $9\times$ better than a previous demonstration of a similar code on superconducting solid-state qubits. Moreover, our implementation exhibits breakeven performance, with some instances achieving qubit lifetimes comparable to or slightly exceeding that of our trapped-ion qubits. We use a novel implementation of the optical-metastable-ground (OMG) architecture for addressable mid-circuit measurement and reset, which enables us to perform these experiments without any ion transport or dedicated coolant ions, requirements that typically consume a large fraction of the runtime or ion count of trapped-ion quantum computers.

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arXiv2026

Fault-Tolerant Quantum Computing with Trapped Ions: The Walking Cat Architecture

We propose a fault-tolerant quantum computer architecture for trapped-ion devices, which we call the walking cat architecture. Our blueprint includes a compiler, a detailed description of all the quantum error-correction protocols, a micro-architecture, a sufficiently fast decoder, and thorough simulations. The backbone of the architecture is a cat factory, producing cat states distributed throughout the machine, which are consumed to perform logical operations. The walking cat architecture is based entirely on a modern quantum error-correction approach called low-density parity-check (LDPC) codes. We identify promising instances of the walking cat architecture, such as (1) a simple architecture based on a single LDPC code, (2) a fast architecture based on fast logical gates relying on a [[70, 6, 9]] code, equipped with Clifford-frame tracking for any 6-qubit Clifford gate, and (3) a dense architecture based on a [[102, 22, 9]]] code encoding 22 logical qubits per memory block. Our dense architecture provides a design with 110 logical qubits executing about one million T gates per day using only 2,514 physical qubits. We estimate that the quantum Hamiltonian simulation of a Heisenberg model on 100 sites can be executed within one month with 10,000 physical qubits, including all shots required to achieve chemical accuracy, suggesting that such a device could enter the regime of classically intractable physics simulations. Our design relies on hardware components that have been experimentally demonstrated on small devices. We emphasize simplicity over hypothetical performance to facilitate the practical realization of this machine. Based on this approach, we believe that a fault-tolerant quantum computer with hundreds of logical qubits capable of running millions of logical gates can be built in the near term, providing a platform to explore a broad range of applications.

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arXiv2025

Recursive Clifford noise reduction

Clifford noise reduction (CliNR) is a partial error correction scheme that reduces the logical error rate of Clifford circuits at the cost of a modest qubit and gate overhead. The CliNR implementation of an $n$-qubit Clifford circuit of size $s$ achieves a vanishing logical error rate if $snp^2\rightarrow 0$ where $p$ is the physical error rate. Here, we propose a recursive version of CliNR that can reduce errors on larger circuits with a relatively small gate overhead. When $np \rightarrow 0$, the logical error rate can be vanishingly small. This implementation requires $\left(2\left\lceil \log(sp)\right\rceil+3\right)n+1$ qubits and at most $24 s \left\lceil(sp)^4\right\rceil $ gates. Using numerical simulations, we show that the recursive method can offer an advantage in a realistic near-term parameter regime. When circuit sizes are large enough, recursive CliNR can reach a lower logical error rate than the original CliNR with the same gate overhead. The results offer promise for reducing logical errors in large Clifford circuits with relatively small overheads.

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arXiv2025

Cyclic Hypergraph Product Code

Hypergraph product (HGP) codes are one of the most popular family of quantum low-density parity-check (LDPC) codes. Circuit-level simulations show that they can achieve the same logical error rate as surface codes with a reduced qubit overhead. They have been extensively optimized by importing classical techniques such as the progressive edge growth, or through random search, simulated annealing or reinforcement learning techniques. In this work, instead of machine learning (ML) algorithms that improve the code performance through local transformations, we impose additional global symmetries, that are hard to discover through ML, and we perform an exhaustive search. Precisely, we focus on the hypergraph product of two cyclic codes, which we call CxC codes and we study C2 codes which are the product a cyclic code with itself and CxR codes which are the product of a cyclic codes with a repetition code. We discover C2 codes and CxR codes that significantly outperform previously optimized HGP codes, achieving better parameters and a logical error rate per logical qubit that is up to three orders of magnitude better. Moreover, some C2 codes achieve simultaneously a lower logical error rate and a smaller qubit overhead than state-of-the-art LDPC codes such as the bivariate bicycle codes, at the price of a larger block length. Finally, leveraging the cyclic symmetry imposed on the codes, we design an efficient planar layout for the QCCD architecture, allowing for a trapped ion implementation of the syndrome extraction circuit in constant depth.

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arXiv2025

Distributed fault-tolerant quantum memories over a 2xL array of qubit modules

We propose an architecture for a quantum memory distributed over a $2 \times L$ array of modules equipped with a cyclic shift implemented via flying qubits. The logical information is distributed across the first row of $L$ modules and quantum error correction is executed using ancilla modules on the second row equipped with a cyclic shift. This work proves that quantum LDPC codes such as BB codes can maintain their performance in a distributed setting while using solely one simple connector: a cyclic shift. We propose two strategies to perform quantum error correction on a $2 \times L$ module array: (i) The cyclic layout which applies to any stabilizer codes, whereas previous results for qubit arrays are limited to CSS codes. (ii) The sparse cyclic layout, specific to bivariate bicycle (BB) codes. For the $[[144,12,12]]$ BB code, using the sparse cyclic layout we obtain a quantum memory with $12$ logical qubits distributed over $12$ modules, containing $12$ physical qubits each. We propose physical implementations of this architecture using flying qubits, that can be faithfully transported, and include qubits encoded in ions, neutral atoms, electrons or photons. We performed numerical simulations when modules are long ion chains and when modules are single-qubit arrays of ions showing that the distributed BB code achieves a logical error rate below $2 \cdot 10^{-6}$ when the physical error rate is $10^{-3}$.

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arXiv2025

Optimized Clifford Noise Reduction: Theory, Simulations and Experiments

We propose several optimizations of the CliNR partial error correction scheme which implements Clifford circuits by consuming a resource state. Errors are corrected by measuring a sequence of Pauli operators that we refer to as the verification sequence. We first propose a global optimization algorithm searching for a verification sequence resulting in a low logical error rate using tabu search. Then, we introduce a proxy for the logical error rate which is easier to evaluate and we design a two-step optimization algorithm. First, a verification sequence minimizing the proxy is computed, then this sequence is refined by reintroducing the logical error rate. Finally, we identify a large group of automorphisms of the search space which preserve the proxy and we use this symmetry to reduce the size of the search space. This results in a 168 $\times$ (respectively 20,160 $\times$) reduction of the size of the search space for the optimization of verification sequences with three (respectively four) Pauli operators. Our numerical simulations for 20-qubit Clifford circuits with size 400 under the ion chain model show that our optimization algorithms improve the performance of CliNR by 25% and that the two-step optimization achieves the same results as the global optimization with 64% fewer evaluations of the logical error rate. Finally, we perform experiments on a 36-qubit trapped ion quantum computer, without mid-circuit measurements, showing that the CZNR variant of CliNR is at breakeven.

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arXiv2024

Low-cost noise reduction for Clifford circuits

We propose a Clifford noise reduction (CliNR) scheme that provides a reduction of the logical error rate of Clifford circuit with lower overhead than error correction and without the exponential sampling overhead of error mitigation. CliNR implements Clifford circuits by splitting them into sub-circuits that are performed using gate teleportation. A few random stabilizer measurements are used to detect errors in the resources states consumed by the gate teleportation. This can be seen as a teleported version of the CPC scheme, with offline fault-detection making it scalable. We prove that CliNR achieves a vanishing logical error rate for families of $n$-qubit Clifford circuits with size $s$ such that $nsp^2$ goes to 0, where $p$ is the physical error rate, meaning that it reaches the regime $ns = o(1/p^2)$ whereas the direct implementation is limited to $s = o(1/p)$. Moreover, CliNR uses only $3n+1$ qubits, $2s + o(s)$ gates and has zero rejection rate. This small overhead makes it more practical than quantum error correction in the near term and our numerical simulations show that CliNR provides a reduction of the logical error rate in relevant noise regimes.

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arXiv2023

Improving Qubit Routing by Using Entanglement Mediated Remote Gates

Near-term quantum computers often have connectivity constraints, i.e. restrictions, on which pairs of qubits in the device can interact. Optimally mapping a quantum circuit to a hardware topology under these constraints is a difficult task. While numerous approaches have been proposed to optimize qubit routing, the resulting gate count and depth overheads of the compiled circuits remain high due to the short-range coupling of qubits in many near-term devices. Resource states, such as Bell or Einstein-Podolsky-Rosen (EPR) pairs, can be used to mediate operations that facilitate long-range interactions between qubits. In this work, we studied some of the practical trade-offs involved in using resource states for qubit routing. We developed a method that leverages an existing state-of-the-art compiler to optimize the routing of circuits with both standard gates and EPR mediated remote controlled-NOT gates. This was then used to compile different benchmark circuits for a square grid topology, where a fraction of the qubits are used to store EPR pairs. We demonstrate that EPR-mediated operations can substantially reduce the total number of gates and depths of compiled circuits when used with an appropriate optimizing compiler that accounts for practical overheads. Our results highlight the relevance of developing efficient compilation tools that can integrate EPR-mediated operations.

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arXiv2023

Variational Quantum Eigensolvers in the Era of Distributed Quantum Computers

The computational power of a quantum computer is limited by the number of qubits available for information processing. Increasing this number within a single device is difficult; it is widely accepted that distributed modular architectures are the solution to large scale quantum computing. The major challenge in implementing such architectures is the need to exchange quantum information between modules. In this work, we show that a distributed quantum computing architecture with {\it limited} capacity to exchange information between modules can accurately solve quantum computational problems. Using the example of a variational quantum eignesolver with an ansatz designed for a two-module (dual-core) architecture, we show that three inter-module operations provide a significant advantage over no inter-module (or serially executed) operations. These results provide a strong indication that near-term {\it modular} quantum processors can be an effective alternative to their monolithic counterparts.

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arXiv2022

Preferred Interaction Ranges in Neutral-Atom Arrays in the Presence of Noise

Successful execution of a quantum information processing (QIP) task on a quantum processing device depends on the availability of high-quality entangling gates. Two important goals in the design and implementation of any entangling gate are low error rates and high connectivity. The former minimizes unintended perturbations to the quantum state during application of that gate, while the latter maximizes the set of qubits that can interact directly without remapping the QIP task through intermediary qubits -- a step that can require many additional gates. Unfortunately, these goals can sometimes conflict, necessitating a careful trade-off. In this work, we study that trade-off in two-dimensional (2D) arrays of neutral atoms interacting through two-qubit gates mediated by the Rydberg blockade effect. The connectivity associated with Rydberg mediated gates on a 2D array is limited by the strength of the Rydberg blockade shift, which decays with distance. Whereas a common strategy to improving connectivity is to use Rydberg levels with larger dipole moments, doing so also leaves the atom more susceptible to electric field noise. Here, we simulate the performance of various logical QIP operations under realistic noise sources and for a variety of Rydberg levels in order to evaluate the connectivity versus gate error trade-off. We find that under many noise regimes, a preferred range of interaction emerges that best satisfies that trade-off. While the exact optimum interaction range depends closely on the details of the atomic implementation, we present simple scaling arguments with broad applicability that should inform future hardware and compiler design choices.

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arXiv2022

Quantum circuit optimization for multiple QPUs using local structure

Interconnecting clusters of qubits will be an essential element of scaling up future quantum computers. Operations between quantum processing units (QPUs) are usually significantly slower and costlier than those within a single QPU, so usage of the interconnect must be carefully managed. This is loosely analogous to the need to manage shared caches or memory in classical multi-CPU machines. Unlike classical clusters, however, quantum data is subject to the no-cloning theorem, which necessitates a rethinking of cache coherency strategies. Here, we consider a simple strategy of using EPR-mediated remote gates and teleporting qubits between clusters as necessary. Crucially, we develop optimizations at compile-time that leverage local structure in a quantum circuit, so as to minimize inter-cluster operations at runtime. We benchmark our approach against existing quantum compilation and optimization routines, and find significant improvements in circuit depth and interconnect usage.

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