arXiv subjects

Ensar Vahapoglu

Publications and source records attributed to Ensar Vahapoglu.

12 recordsLinked to original sources

arXiv2026

Machine Learning for Charge State Characterization of Isolated Double Quantum Dots

Scaling semiconductor quantum dot arrays toward fault-tolerant quantum computing requires efficient tuneup of spin qubits, a process that depends on the analysis of charge stability maps (CSMs) and remains largely manual. While machine learning has been widely applied to CSM analysis in reservoir-coupled devices, automated tuning in the increasingly important isolated-mode regime has received limited attention. In isolated-mode CSMs, charge transitions appear as near-vertical lines, making them well suited to compact, task-specific models. We present two convolutional neural networks with fewer than one million parameters, trained on CSMs collected from 32 silicon metal-oxide-semiconductor (SiMOS) double-quantum-dot devices measured at approximately 1 K using an automated cryogenic probing system. Sixteen devices were used for training and sixteen were held out to evaluate cross-device generalization against hand-labeled ground truth. CSMClassifier identifies charge instability and sensor artifacts, achieving 94% macro-averaged accuracy across three quality classes on 2,407 held-out images. ChargeLineNet localizes charge-transition lines and determines electron occupancy, achieving 95.3% exact line-count accuracy on 1,131 held-out images. Combined into a single pipeline, the models correctly determine electron occupancy for 93.8% of clean held-out images. Pre-training on synthetic images substantially improves label efficiency. Fine-tuning the pre-trained model on limited experimental data maintains over 90% accuracy, whereas training from scratch degrades significantly under the same conditions. Together, the two models occupy only 6.5 MB and process images in less than 60 ms on standard laboratory hardware, demonstrating a practical path toward scalable, automated characterization and tuneup of quantum-dot devices.

cond-mat.mes-hall↗

arXiv2026

Dispersive Readout of a SiMOS Quantum Dot Using a Flip-Chip Integrated Microwave Resonator

Heterogeneous integration provides a promising route to combine semiconductor quantum dot devices and superconducting microwave circuits, while allowing each component to be fabricated using an optimized process flow. Here, we demonstrate a flip-chip integrated platform for dispersive readout of silicon metal-oxide semiconductor (SiMOS) quantum dot devices. A SiMOS double quantum dot chip is bonded to a superconducting aluminum resonator chip using indium bump interconnects to enable microwave coupling to the quantum dot gate. We show that the developed flip-chip process is compatible with cryogenic operation of both the SiMOS device and the superconducting resonator, and demonstrate resonator-based detection of charge transitions in the quantum dot system. The readout signal-to-noise ratio follows a dependence of $\sqrt{t}$ with the integration time, reaching SNR = 1 at an integration time of approximately 0.3 ms. These results establish flip-chip bonding as a viable integration approach for SiMOS quantum dot devices operating at both dc and microwave frequencies, with potential applications for resonator-based techniques such as spin-photon coupling.

cond-mat.mes-hall↗

arXiv2026

SiMOS quantum-dot spin qubits enabled by extreme-ultraviolet lithography

The realization of large-scale silicon quantum processors requires spin qubits compatible with advanced semiconductor manufacturing technologies, demanding lithographic processes that combine nanometer-scale precision with exceptional uniformity. Although the highest-performing silicon spin qubits demonstrated to date have relied on electron-beam (e-beam) lithography, its serial exposure process limits reproducibility studies and wafer-scale fabrication. Here, we demonstrate high-performance silicon metal-oxide-semiconductor (SiMOS) spin qubits fabricated using extreme-ultraviolet (EUV) lithography in a 300 mm semiconductor pilot line. We report wafer-scale quantum-dot uniformity metrics, including 100 % room-temperature gate-to-gate leakage yield and sub-nanometer control of critical gate dimensions. We characterize four double-dot systems realized in two triple-quantum-dot devices. Gate set tomography (GST) reveals consistently high fidelities across all four systems, with values up to 99.8 % for SPAM, 99.9 % for single-qubit gates, and 99.1 % for two-qubit gates. The devices exhibit highly reproducible exchange turn-on characteristics of 10-13 dec/V, indicating high fabrication uniformity enabled by EUV patterning. These results establish EUV lithography as a viable manufacturing technology for quantum processors based on high-fidelity SiMOS spin qubits.

cond-mat.mes-hall↗

arXiv2026

Optimal operating temperature for industry-compatible silicon spin quantum computing: colder is not necessarily better

Silicon spin qubits are a leading candidate for large-scale quantum computing owing to their compatibility with semiconductor manufacturing. However, scaling to useful fault-tolerant processors will likely generate thermal loads that exceed the cooling power available at millikelvin temperatures. Raising the operating temperature eases cooling requirements but reduces gate fidelity, increasing the overhead of quantum error correction. Identifying the operating temperature that minimizes total power consumption is therefore a key challenge for commercially viable quantum computers. Here, we use gate set tomography to benchmark two-qubit silicon chips fabricated in both industrial and academic environments over a range of temperatures. Elevated temperatures substantially shorten coherence times and increase gate and state-preparation-and-measurement infidelities. Based on these measurements, we develop a general power model for silicon quantum computers that combines cryogenic cooling requirements with error-correction overheads. We show that a finite optimal operating temperature exists and is strongly influenced by a crossover temperature near 1 K in current devices, above which gate fidelity degrades rapidly. These results connect device-level fidelity limitations to system-level power requirements, providing design guidelines for large-scale silicon quantum computers.

quant-ph↗

arXiv2026

Gate Stack Engineering for High-Mobility and Low-Noise SiMOS Quantum Devices

We systematically investigate the interplay between materials engineering, quantum transport, and low-frequency charge noise in silicon metal--oxide--semiconductor (SiMOS) quantum devices. By combining Hall-bar transport measurements with charge-noise spectroscopy of gate-defined quantum dots, we identify correlations between gate-stack design, carrier mobility, and electrostatic noise, providing an experimental case study of material and process dependencies relevant to low-noise, high-mobility operation. Hall-bar studies reveal that increasing the atomic-layer-deposition temperature of Al$_2$O$_3$ markedly enhances mobility, whereas the choice of oxidant has little impact. Devices incorporating HfO$_2$ exhibit improved carrier mobility, an interesting observation that can plausibly be attributed to defect passivation associated with aluminum diffusion from the gate metal into the HfO$_2$ layer. Charge-noise measurements show a strong correlation between higher mobility and reduced noise, with TiPd-gated devices displaying both degraded transport and elevated charge noise. In contrast, the poly-Si-gated CMOS-foundry device achieves the lowest noise levels. Finally, dual-feedback dot--sensor stability mapping demonstrates enhanced charge stability in devices with the gate stacks studied here, underscoring their promise for scalable, high-fidelity silicon spin-qubit platforms.

cond-mat.mes-hall↗

arXiv2025

Eight-Qubit Operation of a 300 mm SiMOS Foundry-Fabricated Device

Silicon spin qubits are a promising platform for quantum computing due to their high coherence, controllability, and CMOS manufacturability, yet scalable implementations have so far been limited to a few qubits. Here, to take a step towards larger qubit systems, we tune and coherently control an eight-dot linear array of silicon spin qubits fabricated in a 300~mm CMOS-compatible foundry process, establishing operational scalability beyond the two-qubit regime. All eight qubits are successfully tuned and characterized as four double-dot pairs, exhibiting Ramsey dephasing times $T_2^*$ up to 41(2)$~\mu$s and Hahn-echo coherence times $T_2^{\mathrm{Hahn}}$ up to 1.31(4)$~$ms. Readout of the central four qubits is achieved via a cascaded charge-sensing protocol, enabling high-fidelity measurements of the entire multi-qubit array in a two step process. Additionally, we demonstrate a two-qubit gate operation between adjacent qubits with low phase noise. We show that silicon spin qubit arrays can be scaled to medium-sized arrays of 8 qubits while maintaining system coherence.

quant-ph↗

arXiv2025

Scalable quantum current source on commercial CMOS process technology

Many quantum technologies require a precise electrical current standard that can only be achieved with expensive cryogenics, or through the secondary standards, such as resistance or voltage. Silicon-based charge pumps could provide such a standard in an inherently scalable way, through their compatibility with complementary metal-oxide-semiconductor (CMOS) fabrication methods. However, coherent quantized charge transfer has so far been demonstrated only in nanoscale devices that are custom-fabricated in academic cleanrooms or research technology foundries. Here, we show that a CMOS device manufactured with commercial 22-nm process node can be used to define a quantum current standard in the International System of Units (SI). We measure an accuracy of (1.2 +/- 0.1)E-3 A/A at 50 MHz with reference to SI voltage and resistance standards in a pumped helium system. We then propose a practical monolithic CMOS chip that incorporates one million parallel connected charge pumps along with on-chip control electronics. This chip could be operated as a table-top primary standard that can be easily integrated with CMOS electronics, generating quantum currents of up to microampere levels.

physics.app-ph↗

arXiv2024

Violating Bell's inequality in gate-defined quantum dots

Superior computational power promised by quantum computers utilises the fundamental quantum mechanical principle of entanglement. However, achieving entanglement and verifying that the generated state does not follow the principle of local causality has proven difficult for spin qubits in gate-defined quantum dots, as it requires simultaneously high concurrence values and readout fidelities to break the classical bound imposed by Bell's inequality. Here we employ heralded initialization and calibration via gate set tomography (GST), to reduce all relevant errors and push the fidelities of the full 2-qubit gate set above 99 %, including state preparation and measurement (SPAM). We demonstrate a 97.17 % Bell state fidelity without correcting for readout errors and violate Bell's inequality with a Bell signal of S = 2.731 close to the theoretical maximum of $2\sqrt{2}$. Our measurements exceed the classical limit even at elevated temperatures of 1.1 K or entanglement lifetimes of 100 $\mu s$.

cond-mat.mes-hall↗

arXiv2023

Impact of electrostatic crosstalk on spin qubits in dense CMOS quantum dot arrays

Quantum processors based on integrated nanoscale silicon spin qubits are a promising platform for highly scalable quantum computation. Current CMOS spin qubit processors consist of dense gate arrays to define the quantum dots, making them susceptible to crosstalk from capacitive coupling between a dot and its neighbouring gates. Small but sizeable spin-orbit interactions can transfer this electrostatic crosstalk to the spin g-factors, creating a dependence of the Larmor frequency on the electric field created by gate electrodes positioned even tens of nanometers apart. By studying the Stark shift from tens of spin qubits measured in nine different CMOS devices, we developed a theoretical frawework that explains how electric fields couple to the spin of the electrons in increasingly complex arrays, including those electric fluctuations that limit qubit dephasing times $T_2^*$. The results will aid in the design of robust strategies to scale CMOS quantum technology.

cond-mat.mes-hall↗

arXiv2023

High-fidelity operation and algorithmic initialisation of spin qubits above one kelvin

The encoding of qubits in semiconductor spin carriers has been recognised as a promising approach to a commercial quantum computer that can be lithographically produced and integrated at scale. However, the operation of the large number of qubits required for advantageous quantum applications will produce a thermal load exceeding the available cooling power of cryostats at millikelvin temperatures. As the scale-up accelerates, it becomes imperative to establish fault-tolerant operation above 1 kelvin, where the cooling power is orders of magnitude higher. Here, we tune up and operate spin qubits in silicon above 1 kelvin, with fidelities in the range required for fault-tolerant operation at such temperatures. We design an algorithmic initialisation protocol to prepare a pure two-qubit state even when the thermal energy is substantially above the qubit energies, and incorporate radio-frequency readout to achieve fidelities up to 99.34 per cent for both readout and initialisation. Importantly, we demonstrate a single-qubit Clifford gate fidelity of 99.85 per cent, and a two-qubit gate fidelity of 98.92 per cent. These advances overcome the fundamental limitation that the thermal energy must be well below the qubit energies for high-fidelity operation to be possible, surmounting a major obstacle in the pathway to scalable and fault-tolerant quantum computation.

quant-ph↗

arXiv2023

Bounds to electron spin qubit variability for scalable CMOS architectures

Spins of electrons in CMOS quantum dots combine exquisite quantum properties and scalable fabrication. In the age of quantum technology, however, the metrics that crowned Si/SiO2 as the microelectronics standard need to be reassessed with respect to their impact upon qubit performance. We chart the spin qubit variability due to the unavoidable atomic-scale roughness of the Si/SiO$_2$ interface, compiling experiments in 12 devices, and developing theoretical tools to analyse these results. Atomistic tight binding and path integral Monte Carlo methods are adapted for describing fluctuations in devices with millions of atoms by directly analysing their wavefunctions and electron paths instead of their energy spectra. We correlate the effect of roughness with the variability in qubit position, deformation, valley splitting, valley phase, spin-orbit coupling and exchange coupling. These variabilities are found to be bounded and lie within the tolerances for scalable architectures for quantum computing as long as robust control methods are incorporated.

quant-ph↗

arXiv2019

From Stochastic to Bit Stream Computing: Accurate Implementation of Arithmetic Circuits and Applications in Neural Networks

In this study, we propose a novel computing paradigm "Bit Stream Computing" that is constructed on the logic used in stochastic computing, but does not necessarily employ randomly or Binomially distributed bit streams as stochastic computing does. Any type of streams can be used either stochastic or deterministic. The proposed paradigm benefits from the area advantage of stochastic logic and the accuracy advantage of conventional binary logic. We implement accurate arithmetic multiplier and adder circuits, classified as asynchronous or synchronous; we also consider their suitability of processing successive streams. The proposed circuits are simulated both in gate level and in transistor level with AMS 0.35um CMOS technology to show the circuits' potential for practical use. We thoroughly compare the proposed adders and multipliers with their predecessors in the literature, individually and in a neural network application. Comparisons made in terms of area and accuracy clearly favor the proposed designs. We believe that this study opens up new horizons for computing that enables us to implement much smaller yet accurate arithmetic circuits compared to the conventional binary and stochastic ones.

cs.ET↗