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Erbing Hua

Publications and source records attributed to Erbing Hua.

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From Characterization To Construction: Generative Quantum Circuit Synthesis from Gate Set Tomography Data

High-fidelity circuit execution on noisy intermediate-scale quantum devices is bottlenecked by compilation pipelines that disregard complex, correlated noise. To address this, this methodology article proposes a quantum machine learning control (QMLC) framework for generative quantum circuit synthesis from gate-set tomography (GST) data that bypasses the traditional two-step pipeline of characterizing native quantum gates via GST followed by unitary decomposition algorithms. Instead, a generative concept space is directly learnt from GST data, enabling conditional synthesis of quantum circuits on a desired output distribution. Our approach tokenizes GST germ circuits and embeds them into a structured latent space using a curriculum-learning-motivated strategy, starting with short circuits and progressively incorporating longer ones with diverse output statistics. The embedded sequences are processed by a set-vision transformer with permutation-invariant pooling, producing k-seed vectors that represent the learned concept space of the quantum device. Aggregating data across multiple circuits makes this latent representation inherently context-aware, capturing the shared physical noise environment (e.g., crosstalk, drift) that isolated gate metrics miss. We propose an unconditional diffusion model to sample from the concept space. During inference, a user provides a target measurement distribution, and the model generates a corresponding circuit. To ensure fidelity and robustness, the output is denoised using a diffusion model that operates on the target conditional covariance matrix. This end-to-end framework is a step towards context-aware, hardware-native circuit synthesis directly from raw GST data, which offers a new paradigm for integrating quantum control and compilation. The QMLC framework is particularly suited for near-term quantum devices with complex calibration procedures.

quant-ph

Neural Network Architectures for Scalable Quantum State Tomography: Benchmarking and Memristor-Based Acceleration

Quantum State Tomography (QST) is essential for characterizing and validating quantum systems, but its practical use is severely limited by the exponential growth of the Hilbert space and the number of measurements required for informational completeness. Many prior claims of performance have relied on architectural assumptions rather than systematic validation. We benchmark several neural network architectures to determine which scale effectively with qubit number and which fail to maintain high fidelity as system size increases.To address this, we perform a comprehensive benchmarking of diverse neural architectures across two quantum measurement strategies to evaluate their effectiveness in reconstructing both pure and mixed quantum states. Our results reveal that CNN and CGAN scale more robustly and achieve the highest fidelities, while Spiking Variational Autoencoder (SVAE) demonstrates moderate fidelity performance, making it a strong candidate for embedded, low-power hardware implementations.Recognizing that practical quantum diagnostics will require embedded, energy-efficient computation, we also discuss how memristor-based Computation-in-Memory (CiM) platforms can accelerate these models in hardware, mitigating memory bottlenecks and reducing energy consumption to enable scalable in-situ QST. This work identifies which architectures scale favorably for future quantum systems and lays the groundwork for quantum-classical co-design that is both computationally and physically scalable.

quant-ph

PdNeuRAM: forming-free, multi-bit Pd/HfO2 ReRAM for energy-efficient neuromorphic computing

Memristor technology shows great promise for energy-efficient computing, yet it grapples with challenges like resistance drift and inherent variability. For filamentary Resistive RAM (ReRAM), one of the most investigated types of memristive devices, the expensive electroforming step required to create conductive pathways results in increased power and area overheads and reduced endurance. In this study, we present novel HfO2-based forming-free ReRAM devices, PdNeuRAM, that operate at low voltages, support multi-bit functionality, and display reduced variability. Through a deep understanding and comprehensive material characterization, we discover the key process that allows this unique behavior: a Pd-O-Hf configuration that capitalizes on Pd innate affinity for integrating into HfO2. This structure actively facilitates charge redistribution at room temperature, effectively eliminating the need for electroforming. Moreover, the fabricated ReRAM device provides tunable resistance states for dense memory and reduces programming and reading energy by 43% and 73%, respectively, using spiking neural networks (SNN). This study reveals novel mechanistic insights and delineates a strategic roadmap for the realization of power-efficient and cost-effective ReRAM devices.

cond-mat.mtrl-sci