Eric Beyne | Searcharxiv

arXiv2026

Low Distortion Fusion Bonding using Pneumatically Warped Wafers

Backside power-delivery-network (BSPDN) schemes require wafer-to-wafer bonding steps that do not leave high order shape changes or localized stresses in the bonded stack to ensure that these don't get transferred to the thinned wafer for further lithographic exposure. However, bonding mechanics involve strong adhesive forces which can inherently create localized distortions that lithography tools must eventually compensate. Some contributors to grid distortion of the target wafer are, method of bond initiation, bond front velocity variations, and lack of symmetry between the wafers. In this work, we evaluate a low-distortion bonding approach in the SUSS XBA tool, where some of these contributors are tackled at the source, namely by initiating the bond without a localized external force, and keeping the wafers compliant & symmetric during bonding. Wafers are bonded with a slight pre-stress due to controlled gas pressure applied over the whole backside of the wafers throughout bonding. Wafer-shape measurements of the bonded stacks are used to perform gradient-based in-plane-displacements (IPD) modelling to estimate bonding-induced grid distortion. Dense scanner metrology is used on patterned-bonded wafers to confirm the location and severity of distortion predictions from patterned wafer geometry (PWG) measurements. On the PWG distortion maps and scanner grid readouts, we perform alignment and CPE modelling with different field layouts. Sub-10 nm levels of residual grid distortion are achievable with relatively low-order correction models, and less than or equal to 3 nm by using advanced CPE models. These results demonstrate that pneumatically warped bonding yields low-distortion bonded stacks, and that simple process tuning can decouple the dominant distortion source from edge-related variability.

physics.app-ph↗

arXiv2023

Impact of gate-level clustering on automated system partitioning of 3D-ICs

When partitioning gate-level netlists using graphs, it is beneficial to cluster gates to reduce the order of the graph and preserve some characteristics of the circuit that the partitioning might degrade. Gate clustering is even more important for netlist partitioning targeting 3D system integration. In this paper, we make the argument that the choice of clustering method for 3D-ICs partitioning is not trivial and deserves careful consideration. To support our claim, we implemented three clustering methods that were used prior to partitioning two synthetic designs representing two extremes of the circuits medium/long interconnect diversity spectrum. Automatically partitioned netlists are then placed and routed in 3D to compare the impact of clustering methods on several metrics. From our experiments, we see that the clustering method indeed has a different impact depending on the design considered and that a circuit-blind, universal partitioning method is not the way to go, with wire-length savings of up to 31%, total power of up to 22%, and effective frequency of up to 15% compared to other methods. Furthermore, we highlight that 3D-ICs open new opportunities to design systems with a denser interconnect, drastically reducing the design utilization of circuits that would not be considered viable in 2D.

cs.AR↗