arXiv subjects

Eric Pop

Publications and source records attributed to Eric Pop.

At least 19 recordsLinked to original sources

arXiv2026

Cross-Domain Acceleration of Open Modification Search: From Commodity Platforms to Emerging Memory and Storage Devices

Open modification search (OMS) in mass spectrometry (MS) is a data-intensive workload whose performance is dominantly limited by reference data movement rather than computation. Prior OMS accelerators have largely been evaluated in isolation, making it difficult to understand system-level trade-offs across platforms. This paper presents the first workload-driven, cross-platform survey of accelerators for MS search by studying not only commodity platforms, but also emerging memory- and storage-centric architectures, including GPUs, near-storage FPGAs, DRAM near-memory processing, ReRAM/PCM in-memory processing, and 3D NAND/FeNAND in-storage processing, under consistent algorithmic and accuracy assumptions. Leveraging a binary hyperdimensional computing (HDC)-based OMS formulation that reduces similarity evaluation to lightweight bitwise primitives and tolerates device-level non-idealities, we enable a robust execution on memory-centric architectures despite device-level non-idealities and limited computing capability. Overall, this study identifies memory- and storage-centric architectures as a key architectural breakthrough for large-scale, high-speed search acceleration, delivering up to >100x speedup and >40,000x improvement in energy efficiency.

cs.AR↗

arXiv2026

Energy and Scaling Limits of Phase-Change Memory

Phase change memory (PCM) relies on a reversible transition between amorphous and crystalline states of a material, and stands as a promising candidate for next-generation, energy-efficient data storage and neuromorphic hardware. Here, we review key innovations that have driven PCM technology to achieve energy consumption down to only tens of femtojoules per bit, and could further advance it closer to its fundamental limits. Because PCM switching is induced thermally, we highlight improvements in energy-efficiency through two primary strategies: by minimizing the active phase change material region to sub-10 nm dimensions, and by enhancing heat confinement within PCM devices to reduce thermal dissipation into the surrounding environment. While the theoretical limits could reach single attojoules per cubic nanometer of memory material, realizing these limits in practice is significantly constrained by electrical and thermal parasitics, particularly at contacts and interfaces.

cond-mat.mtrl-sci↗

arXiv2025

Channel-last gate-all-around nanosheet oxide semiconductor transistors

As we move beyond the era of transistor miniaturization, back-end-of-line-compatible transistors that can be stacked monolithically in the third dimension promise improved performance for low-power electronics. In advanced transistor architectures, such as gate-all-around nanosheets, the conventional channel-first process involves depositing dielectrics directly onto the channel. Atomic layer deposition of gate dielectrics on back-end-of-line compatible channel materials, such as amorphous oxide semiconductors, can induce defects or cause structural modifications that degrade electrical performance. While post-deposition annealing can partially repair this damage, it often degrades other device metrics. We report a novel channel-last concept that prevents such damage. Channel-last gate-all-around self-aligned transistors with amorphous oxide-semiconductor channels exhibit high on-state current ($>$ 1 mA/$\mu$m) and low subthreshold swing (minimum of 63 mV/dec) without the need for post-deposition processing. This approach offers a general, scalable pathway for transistors with atomic layer deposited channel materials, enabling the future of low-power three-dimensional electronics.

cond-mat.mtrl-sci↗

arXiv2025

Gate Dielectric Engineering with an Ultrathin Silicon-oxide Interfacial Dipole Layer for Low-Leakage Oxide-Semiconductor Memories

We demonstrate a gate dielectric engineering approach leveraging an ultrathin, atomic layer deposited (ALD) silicon oxide interfacial layer (SiL) between the amorphous oxide semiconductor (AOS) channel and the high-k gate dielectric. SiL positively shifts the threshold voltage (V$_T$) of AOS transistors, providing at least four distinct $V_T$ levels with a maximum increase of 500 mV. It achieves stable $V_T$ control without significantly degrading critical device parameters such as mobility, on-state current, all while keeping the process temperature below 225 $^{\circ}$C and requiring no additional heat treatment to activate the dipole. Positive-bias temperature instability tests at 85 $^{\circ}$C indicate a significant reduction in negative $V_{T}$ shifts for SiL-integrated devices, highlighting enhanced reliability. Incorporating this SiL gate stack into two-transistor gain-cell (GC) memory maintains a more stable storage node voltage ($V_{SN}$) (reduces $V_{SN}$ drop by 67\%), by limiting unwanted charge losses. SiL-engineered GCs also reach retention times up to 10,000 s at room temperature and reduce standby leakage current by three orders of magnitude relative to baseline device, substantially lowering refresh energy consumption.

cond-mat.mtrl-sci↗

arXiv2025

How to Identify Suitable Gate Dielectrics for Transistors based on Two-Dimensional Semiconductors

The recent progress in nanosheet transistors has established two-dimensional (2D) semiconductors as viable candidates for future ultra-scaled electronic devices. Next to reducing contact resistance, identifying good gate dielectrics is a fundamental challenge, as the dielectric/channel interface dramatically impacts virtually all performance parameters. While several promising gate dielectrics have recently been reported, the evaluation of their quality and suitability is often fragmentary and focused on selected important performance metrics of the gate stack, such as the capacitive gate control, leakage currents, reliability, and ease of fabrication and integration. However, identifying a suitable gate stack is a complex problem that has not yet been approached systematically. In this perspective, we aim to formulate general criteria for good gate dielectrics.

physics.app-ph↗

arXiv2025

Scaling Nanoribbon Transistors with Monolayer Transition Metal Dichalcogenides

Nanoscale transistors require aggressive reduction of all channel dimensions: length, width, and thickness. While monolayer two-dimensional semiconductors (2DS) offer ultimate thickness scaling, good performance has largely been achieved only in micrometer-wide channels. Here, we demonstrate both $\it{n}$- and $\it{p}$-type nanoribbon transistors based on monolayer 2DS, fabricated using a multi-patterning process, reaching channel widths and lengths down to 25-30 nm. 'Anchored' contacts improve device yield, while nanoscale imaging, including tip-enhanced photoluminescence, reveals minimal edge degradation. The devices reach on-state currents up to 560, 420, and 130 $\mu$A $\mu$m$^{-1}$ at 1 V drain-to-source voltage for $\it{n}$-type MoS$_{2}$, WS$_{2}$, and $\it{p}$-type WSe$_{2}$, respectively, integrated with thin high-$\kappa$ dielectrics. These results surpass prior reports for single-gated nanoribbons, the WS$_{2}$ by over 100 times, even in normally off (enhancement-mode) transistors. Taken together, these findings suggest that top down patterned 2DS nanoribbons are promising building blocks for future nanosheet transistors.

cond-mat.mtrl-sci↗

arXiv2025

High-current p-type transistors from precursor-engineered synthetic monolayer WSe$_2$

Monolayer tungsten diselenide (WSe$_2$) is a leading candidate for nanoscale complementary logic. However, high defect densities introduced during thin-film growth and device fabrication have limited p-type transistor performance. Here, we report a combined strategy of precursor-engineered chemical vapor deposition and damage-minimizing fabrication to overcome this limitation. By converting tungsten trioxide and residual oxyselenides into reactive suboxides before growth, and precisely regulating selenium delivery during deposition, we synthesize uniform, centimeter-scale monolayer WSe$_2$ films with charged defect densities as low as $5 \times 10^{9}$ cm$^{-2}$. Transistors fabricated from these films achieve record p-type on-state current up to $888 \mu$A$\cdot\mu$m$^{-1}$ at $V_{\mathrm{DS}}=-1$ V, matching leading n-type devices. This leap in material quality closes the p-type performance gap without exotic doping or contact materials, marking a critical step towards complementary two-dimensional semiconductor circuits.

cond-mat.mtrl-sci↗

arXiv2025

Deep Learning to Automate Parameter Extraction and Model Fitting of Two-Dimensional Transistors

We present a deep learning approach to extract physical parameters (e.g., mobility, Schottky contact barrier height, defect profiles) of two-dimensional (2D) transistors from electrical measurements, enabling automated parameter extraction and technology computer-aided design (TCAD) fitting. To facilitate this task, we implement a simple data augmentation and pre-training approach by training a secondary neural network to approximate a physics-based device simulator. This method enables high-quality fits after training the neural network on electrical data generated from physics-based simulations of ~500 devices, a factor >40$\times$ fewer than other recent efforts. Consequently, fitting can be achieved by training on physically rigorous TCAD models, including complex geometry, self-consistent transport, and electrostatic effects, and is not limited to computationally inexpensive compact models. We apply our approach to reverse-engineer key parameters from experimental monolayer WS$_2$ transistors, achieving a median coefficient of determination ($R^2$) = 0.99 when fitting measured electrical data. We also demonstrate that this approach generalizes and scales well by reverse-engineering electrical data on high-electron-mobility transistors while fitting 35 parameters simultaneously. To facilitate future research on deep learning approaches for inverse transistor design, we have published our code and sample data sets online.

cs.LG↗

arXiv2025

Wide-field Hyperspectral Optical Microscopy for Rapid Characterization of Two-Dimensional Semiconductors and Heterostructures

Electronic and optoelectronic applications of two-dimensional (2D) semiconductors demand precise control over material quality, including thickness, composition, doping, and defect density. Conventional benchmarking methods (e.g., charge transport, confocal mapping, electron or scanning probe microscopy) are slow, perturb sample quality, or involve trade-offs between speed, resolution, and scan area. To accelerate assessment of 2D semiconductors, we demonstrate a broadband, wide-field hyperspectral optical microscope for 2D materials (2D-HOM) that rapidly captures a spatial-spectral data cube within seconds. The data cube includes x-y spatial coordinate (a 300 * 300 $\mu\mathrm{m}^2$ field, with ~ 1 $\mu\mathrm{m}$ resolution) and a selectable wavelength range between 1100 to 200 nm at each pixel. Using synthesized films and heterostructures of transition metal dichalcogenides ($\mathrm{MoS}_{2}$, $\mathrm{WS}_{2}$, $\mathrm{V}_{x}\mathrm{W}_{1-x}\mathrm{S}_{2}$, and $\mathrm{WSe}_{2}$), we show that this cost-effective technique detects spectral fingerprints of material identity, doping, grain boundaries, and alloy composition, and enables advanced analysis, including unsupervised machine learning for spatial segmentation.

cond-mat.mtrl-sci↗

arXiv2025

Low Resistance P-type Contacts to Monolayer WSe$_2$ through Chlorinated Solvent Doping

Tungsten diselenide (WSe$_2$) is a promising p-type semiconductor limited by high contact resistance ($R_\textrm{C}$) and the lack of a reliable doping strategy. Here, we demonstrate that exposing WSe$_2$ to chloroform provides simple and stable p-type doping. In monolayer WSe$_2$ transistors with Pd contacts, chloroform increases the maximum hole current by over 100$\times$ (>200 $\mu$A/$\mu$m), reduces $R_\textrm{C}$ to ~2.5 k$\Omega\cdot\mu$m, and retains an on/off ratio of $10^{10}$ at room temperature. These improvements persist for over 8 months, survive annealing above 150 {\deg}C, and remain effective down to 10 K, enabling a cryogenic $R_\textrm{C}$ of ~1 k$\Omega\cdot\mu$m. Density functional theory indicates that chloroform strongly physisorbs to WSe$_2$, inducing hole doping with minimal impact on the electronic states between the valence band and conduction band edges. Auger electron spectroscopy and atomic force microscopy reveal that chloroform intercalates at the WSe$_2$ interface with the gate oxide, contributing to doping stability and mitigating interfacial dielectric disorder. This robust, scalable approach enables high-yield WSe$_2$ transistors with good p-type performance.

cond-mat.mtrl-sci↗

arXiv2025

Synthesis-related nanoscale defects in Mo-based Janus monolayers revealed by cross-correlated AFM and TERS imaging

Two-dimensional (2D) Janus transition metal dichalcogenides (TMDs) are promising candidates for various applications in non-linear optics, energy harvesting, and catalysis. These materials are usually synthesized via chemical conversion of pristine TMDs. Nanometer-scale characterization of the obtained Janus materials' morphology and local composition is crucial for both the synthesis optimization and the future device applications. In this work, we present a cross-correlated atomic force microscopy (AFM) and tip-enhanced Raman spectroscopy (TERS) study of Janus $\mathrm{Mo}_{\mathrm{Se}}^{\mathrm{S}}$ and Janus $\mathrm{Mo}_{\mathrm{S}}^{\mathrm{Se}}$ monolayers synthesized by the hydrogen plasma-assisted chemical conversion of $\mathrm{MoSe}_2$ and $\mathrm{MoS}_2$, respectively. We demonstrate how the choice of the growth substrate and the starting TMD affects the morphology of the resulting Janus material. Furthermore, by employing TERS imaging, we demonstrate the presence of nanoscale islands (~20 nm across) of $\mathrm{MoSe}_2$-$\mathrm{Mo}_{\mathrm{Se}}^{\mathrm{S}}$ ($\mathrm{MoS}_2$-$\mathrm{Mo}_{\mathrm{S}}^{\mathrm{Se}}$) vertical heterostructures originating from the bilayer nanoislands in the precursor monolayer crystals. The understanding of the origins of nanoscale defects in Janus TMDs revealed in our study can help with further optimization of the Janus conversion process towards uniform and wrinkle-/crack-free Janus materials. Moreover, our work shows that cross-correlated AFM and TERS imaging is a powerful and accessible method for studying nanoscale composition and defects in Janus TMD monolayers.

cond-mat.mtrl-sci↗

arXiv2025

Flexible radiofrequency carbon nanotube transistors operating at frequencies above 100 GHz

The development of the sixth generation of wireless communications technology (6G) requires terminals that can operate at frequencies above 100 GHz. For human-centric applications, these terminals should also be flexible and have low power. However, current flexible radiofrequency transistors typically have lower maximum frequencies, in part due to the poor thermal conductivity of flexible substrates. Here, we report radiofrequency transistors that are based on aligned carbon nanotube arrays on flexible substrates and have current gain cutoff frequencies ($f_{\text{T}}$) and power gain cutoff frequencies ($f_{\text{max}}$) above 100 GHz. This is achieved by using electro-thermal co-design to improve the heat dissipation and radiofrequency performance of the devices. The transistors exhibit an on-state current of 0.947 mA $\mu$m$^{-1}$, a transconductance of 0.728 mS $\mu$m$^{-1}$, a peak extrinsic $f_{\text{T}}$ of 152 GHz, a peak extrinsic $f_{\text{max}}$ of 102 GHz, and a power consumption under 200 mW mm$^{-1}$. We also show that the devices can be used to create flexible radiofrequency amplifiers with an output power of 64 mW mm$^{-1}$ and a 11 dB power gain in the K-band.

physics.app-ph↗

arXiv2025

High-field Breakdown and Thermal Characterization of Indium Tin Oxide Transistors

Amorphous oxide semiconductors are gaining interest for logic and memory transistors compatible with low-temperature fabrication. However, their low thermal conductivity and heterogeneous interfaces suggest that their performance may be severely limited by self-heating, especially at higher power and device densities. Here, we investigate the high-field breakdown of ultrathin (~4 nm) amorphous indium tin oxide (ITO) transistors with scanning thermal microscopy (SThM) and multiphysics simulations. The ITO devices break irreversibly at channel temperatures of ~180 {\deg}C and ~340 {\deg}C on SiO${_2}$ and HfO${_2}$ substrates, respectively, with failure primarily caused by thermally-induced compressive strain near the device contacts. Combining SThM measurements with simulations allows us to estimate a thermal boundary conductance (TBC) of 35 ${\pm}$ 12 MWm${^-}$${^2}$K${^-}$${^1}$ for ITO on SiO${_2}$, and 51 ${\pm}$ 14 MWm${^-}$${^2}$K${^-}$${^1}$ for ITO on HfO${_2}$. The latter also enables significantly higher breakdown power due to better heat dissipation and closer thermal expansion matching. These findings provide insights into the thermo-mechanical limitations of indium-based amorphous oxide transistors, which are important for more reliable and high-performance logic and memory applications.

physics.app-ph↗

arXiv2024

Direct X-Ray Measurements of Strain in Monolayer MoS$_{2}$ from Capping Layers and Geometrical Features

Strain induced through fabrication, both by patterning and capping, can be used to change the properties of two-dimensional (2D) materials or other thin films. Here, we explore how capping layers impart strain to monolayer MoS$_{2}$ using direct x-ray diffraction measurements of the lattice. We first observe the impact of naturally-oxidized metal layers ($\sim$1.5 nm Al) and subsequently-deposited Al$_{2}$O$_{3}$ (15 nm to 25 nm thick) on the 2D material, and find that the strain imparted to MoS$_{2}$ is mainly controlled by the interfacial adhesion of the seed layer in addition to the substrate adhesion. Then, using test structures which mimic transistor contacts, we measure enhanced strain from such patterns compared to blanket films. Furthermore, we observe significant tensile strain - up to 2% in monolayer MoS$_{2}$, one of the largest experimental values to date on a rigid substrate - due to highly-stressed blanket metal capping layers. These results provide direct evidence supporting previous reports of strain effects in 2D material devices.

cond-mat.mtrl-sci↗

arXiv2024

SpecPCM: A Low-power PCM-based In-Memory Computing Accelerator for Full-stack Mass Spectrometry Analysis

Mass spectrometry (MS) is essential for proteomics and metabolomics but faces impending challenges in efficiently processing the vast volumes of data. This paper introduces SpecPCM, an in-memory computing (IMC) accelerator designed to achieve substantial improvements in energy and delay efficiency for both MS spectral clustering and database (DB) search. SpecPCM employs analog processing with low-voltage swing and utilizes recently introduced phase change memory (PCM) devices based on superlattice materials, optimized for low-voltage and low-power programming. Our approach integrates contributions across multiple levels: application, algorithm, circuit, device, and instruction sets. We leverage a robust hyperdimensional computing (HD) algorithm with a novel dimension-packing method and develop specialized hardware for the end-to-end MS pipeline to overcome the non-ideal behavior of PCM devices. We further optimize multi-level PCM devices for different tasks by using different materials. We also perform a comprehensive design exploration to improve energy and delay efficiency while maintaining accuracy, exploring various combinations of hardware and software parameters controlled by the instruction set architecture (ISA). SpecPCM, with up to three bits per cell, achieves speedups of up to 82x and 143x for MS clustering and DB search tasks, respectively, along with a four-orders-of-magnitude improvement in energy efficiency compared with state-of-the-art CPU/GPU tools.

cs.AR↗

arXiv2024

Transition Metal Dichalcogenide Solar Cells for Indoor Energy Harvesting

With the rapid expansion of the Internet of Things (IoT), efficient and durable energy harvesters for powering IoT devices operating indoors and outdoors are imperative. Promising materials for indoor photovoltaic (PV) technologies include transition metal dichalcogenides (TMDs) such as MoS2, MoSe2, WS2, and WSe2, mainly due to their high absorption coefficients and self-passivated surfaces. Here, we assess the performance of single-junction TMD solar cells under various indoor lighting conditions with a realistic detailed balance model including material-specific optical absorption, as well as radiative, Auger, and defect-assisted Shockley-Read-Hall recombination. We find TMD solar cells could achieve up to 36.5%, 35.6%, 11.2%, and 27.6% power conversion efficiency under fluorescent, LED, halogen, and low-light AM 1.5 G lighting, respectively, at 500 lux. Based on this, TMD solar cells could outperform commercial PV technologies in indoor scenarios, suggesting their viability for future IoT energy solutions.

cond-mat.mtrl-sci↗

arXiv2024

Enabling P-type Conduction in Bilayer WS2 with NbP Topological Semimetal Contacts

Two-dimensional (2D) semiconductors are promising for low-power complementary metal oxide semiconductor (CMOS) electronics, which require ultrathin n- and p-type transistor channels. Among 2D semiconductors, WS2 is expected to have good conduction for both electrons and holes, but p-type WS2 transistors have been difficult to realize due to the relatively deep valence band and the presence of mid-gap states with conventional metal contacts. Here, we report topological semimetal NbP as p-type electrical contacts to bilayer WS2 with up to 5.8 microamperes per micron hole current at room temperature; this is the highest to date for sub 2 nm thin WS2 and more than 50 times larger than with metals like Ni or Pd. The p-type conduction is enabled by the simultaneously high work function and low density of states of the NbP, which reduce Fermi level pinning. These contacts are sputter-deposited at room temperature, an approach compatible with CMOS fabrication, a step towards enabling ultrathin WS2 semiconductors in future nanoelectronics.

cond-mat.mtrl-sci↗

arXiv2024

Surface conduction and reduced electrical resistivity in ultrathin noncrystalline NbP semimetal

The electrical resistivity of conventional metals, such as copper, is known to increase in thin films due to electron-surface scattering, limiting the performance of metals in nanoscale electronics. Here, we find an unusual reduction of resistivity with decreasing film thickness in niobium phosphide (NbP) semimetal deposited at relatively low temperatures of 400 \deg C. In films thinner than 5 nm, the room temperature resistivity (~34 microohm*cm for 1.5-nm-thick NbP) was up to six times lower than the bulk NbP resistivity, and lower than conventional metals at similar thickness (typically ~100 microohm*cm). Remarkably, the NbP films are not crystalline, but display local nanocrystalline, short-range order within an amorphous matrix. Our analysis suggests that the lower effective resistivity is due to conduction via surface channels, together with high surface carrier density and sufficiently good mobility as the film thickness is reduced. These results and the fundamental insights obtained here could enable ultrathin, low-resistivity wires for nanoelectronics, beyond the limitations of conventional metals.

cond-mat.mtrl-sci↗