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Erik P. DeBenedictis

Publications and source records attributed to Erik P. DeBenedictis.

3 recordsLinked to original sources

Kinetic Inductors Enable Reversible Logic

Reversible logic has long promised substantial reductions in energy dissipation, yet prior demonstrations have not scaled to commercially relevant systems. This work presents a quantitative framework for evaluating reversible logic through a process termed CMOS conversion, in which a conventional CMOS design is transformed into a functionally equivalent reversible implementation and compared using common performance metrics. The framework combines planning equations, kinetic-inductor energy-storage models, a four-phase 4LC energy-recycling power supply, and RLC-based simulation methods that account for data-dependent loading effects. The analysis identifies inductor loss as a fundamental limitation of conventional approaches and shows that high-energy-density kinetic inductors provide essential design margin for scaling reversible systems. Using representative device parameters, the framework suggests that selected cryogenic CMOS qubit controller circuits could be converted to reversible logic using available or near-term technologies. Rather than claiming commercialization of reversible logic in general, the paper provides a methodology for assessing its feasibility and potential benefits across future applications.

cs.ET↗

Scaling up Reversible Logic with HKI Superconducting Inductors

Researchers developed about a dozen semiconductor reversible (or adiabatic) logic chips since the early 1990s, validating circuit designs and proving the concept--but scale up required a further advance. This document shows that cryogenic inductors made of a new High Kinetic Inductance (HKI) material provide the advance. This material can be deposited as an integrated circuit layer, where it has enough energy recycling capacity to power a reversible circuit of the same size. This allows a designer to replicate and scale a complete reversible logic subsystem in accordance with Moore's law.

cs.ET↗

Quantum Computer Control using Novel, Hybrid Semiconductor-Superconductor Electronics

Inspired by recent interest in quantum computing and recent studies of cryo CMOS for control electronics, this paper presents a hybrid semiconductor-superconductor approach for engineering scalable computing systems that operate across the gradient between room temperature and the temperature of a cryogenic payload. Such a hybrid computer architecture would have unique suitability to quantum computers, scalable sensors, and the quantum internet. The approach is enabled by Cryogenic Adiabatic Transistor Circuits (CATCs), a novel way of using adiabatic circuits to substantially reduce cooling requirements. In a hybrid chip of CATCs and a second technology, such as Josephson junctions (JJs) or cryo CMOS, the CATCs complement the speed, power, and density of the second technology as well as becoming a longsought cryogenic memory. This paper describes higher-level design principles for CATC hybrids with a quantum computer control system that includes CATC memory, an FPGA-like logic module that uses CATC for dense configuration logic and JJs for fast configured logic, and I/O subsystems including microwave modulators and low frequency control signals.

quant-ph↗