arXiv subjects

Evan B. Golden

Publications and source records attributed to Evan B. Golden.

14 recordsLinked to original sources

arXiv2025

Demonstration of Superconductor Shift Registers with Energy Dissipation Below Landauer's Thermodynamic Limit

We study energy dissipation and propagation of information encoded by Josephson vortices in two types of circular shift register: a) a uniform register composed of sections of discrete Josephson transmission lines (JTL) forming a closed loop with a flux pump allowing to change the number of moving fluxon; b) a nonuniform register composed of sections of the regular JTL and sections of JTLs utilizing nSQUIDs - dc-SQUIDs with negative inductance between their arms - instead of single Josephson junctions. nSQUIDs are parametric devices with a flexible double-well potential that were proposed as components for reversible computing. For the uniform register, we demonstrate the energy dissipation per bit-shift operation below the Landauer's thermodynamic limit $E_T=k_BTln2$ up to propagation delays of ~0.7 ns, corresponding to the circular information motion with frequencies up to ~1.4 GHz. This does not contradict Landauer's minimum energy requirement for computations since information is not destroyed. For the nonuniform register, we find the minimum energy dissipation per bit-shift of about 16$E_T$ and attribute this to a nonuniform movement of vortices and energy barriers between the regular JTL and nSQUID sections. Differences of Josephson vortex propagation in both types of circular registers are discussed based on the measured current-voltage characteristics, extracted effective resistance and the terminal speed of Josephson vortices, and their dependences on the number of moving vorticies. nSQUID inductance connecting JJs to the ground leads to an unusual type of lossless discrete transmission line with frequency-dependent impedance and propagation speed, both different from the regular JTLs.

cond-mat.supr-con↗

arXiv2025

Fabrication and Properties of NbN/NbNx/NbN and Nb/NbNx/Nb Josephson Junctions

Increasing integration scale of superconductor electronics (SCE) requires employing kinetic inductors and self-shunted Josephson junctions (JJs) for miniaturizing inductors and JJs. We have been developing a ten-superconductor-layer planarized fabrication process with NbN kinetic inductors and searching for suitable self-shunted JJs to potentially replace high Josephson critical current density, Jc, Nb/Al-AlOx/Nb junctions. We report on the fabrication and electrical properties of NbN/NbNx/NbN junctions produced by reactive sputtering in Ar+N2 mixture on 200-mm wafers at 200 oC and incorporated into a planarized process with two Nb ground planes and Nb wiring layer. Here NbN is a stoichiometric nitride with superconducting critical temperature Tc =15 K and NbNx is a high resistivity, nonsuperconducting nitride deposited using a higher nitrogen partial pressure than for the NbN electrodes. For comparison, we co-fabricated Nb/NbNx/Nb JJs using the same NbNx barriers deposited at 20 oC. We varied the NbNx barrier thickness from 5 nm to 20 nm, resulting in the range of Jc from about 1 mA/um^2 down to ~10 uA/um^2, and extracted coherence length of 3 nm and 4 nm in NbNx deposited, respectively at 20 oC and 200 oC. Both types of JJs are well described by resistively and capacitively shunted junction model without any excess current. We found the Jc of NbN/NbNx/NbN JJs to be somewhat lower than of Nb/NbNx/Nb JJs with the same barrier thickness, despite a much higher Tc and energy gap of NbN than of Nb electrodes. IcRn products up to ~ 0.5 mV were obtained for JJs with Jc~ 0.6 mA/um^2. Jc(T) dependences have been measured.

cond-mat.supr-con↗

arXiv2025

Characterization of Flux Trapping in and Fabrication of Large-Scale Superconductor Circuits Using AC-Biased Shift Registers With 108500 Josephson Junctions

A variety of superconductor integrated circuits comprising six ac-powered SFQ shift registers with a total of 27078 bits and 108500 Josephson junctions (JJs) per 5 mm x 5 mm chip have been designed, fabricated, and tested to characterize flux trapping, fabrication process yield, and parameter spread. The six 4513-bit registers in the circuits have a common single-phase ac clock and individual input/output drivers enabling their parallel testing. We have investigated flux trapping in the circuits with various geometry, size, and distance between moats in two active ground planes (GPs), and containing up to three additional 'dummy' GPs, using multiple cooldowns through the critical temperature with various cooling rates and residual magnetic fields up to ~1.2 $μ$T. For the slit-type and square moats arrayed along the sides of the register cells, we have found a negligible effect of flux sequestered in the moats on the operating margins of the registers, and negligible probability of detrimental flux trapping outside of the moats. Circuits with 0.3-$μ$m-wide slit moats occupying <2% of the circuit area were fully operational in 100% of cooldowns, supporting the viability of VLSI superconductor digital circuits. We have found a strong enhancement of flux trapping outside of the moats in circuits with closely spaced GPs and determined a critical distance, t$_c$=0.6 $μ$m, between them. The presence of GPs spaced below t$_c$ rendered the circuits nonoperational in 100% of cooldowns. We have measured 30 chips with >3M JJs and determined individual cell margins in 138 registers to characterize the fabrication-related parameter spread and detect fabrication defects and flux-trapping events. By finding outlier cells in the statistical distribution of the individual cell margins, we detected about one defect per million JJs, in most cases causing magnetic flux trapping in the affected cell.

cond-mat.supr-con↗

arXiv2024

Development of a Neuromorphic Network Using BioSFQ Circuits

Superconductor electronics (SCE) appear promising for low energy applications. However, the achieved and projected circuit densities are insufficient for direct competition with CMOS technology. Original algorithms and nontraditional architectures are required for realizing SCE energy advantages for computing. Neuromorphic computing (NMC) is a commonly discussed deviation from conventional CMOS digital solutions. Instead of mimicking a conventional network of artificial neurons, we compose a network from the previously demonstrated single flux quantum (SFQ) electronics components which we termed bioSFQ. We present a design and operation of a new neuromorphic circuit containing a 3x3 array of bioSFQ cells - superconductor artificial neurons - capable of performing various analog functions and based on Josephson junction comparators with complementary outputs. The resultant asynchronous network closely resembles a three-layer perceptron. We also present superconductor analog memory and the memory Read/Write interface implemented with the neural network. The circuits were fabricated in the SFQ5ee process at MIT Lincoln Laboratory.

cond-mat.supr-con↗

arXiv2024

Characterization of Adiabatic Quantum-Flux-Parametrons in the MIT LL SFQ5ee+ Process

Adiabatic quantum-flux-parametron (AQFP) logic is a proven energy-efficient superconductor technology for various applications. To address the scalability challenges, we investigated AQFP shift registers with the AQFP footprint area reduced by 25% with respect to prior work and with more than 2x denser overall designs obtained by eliminating the previously used free space between the AQFPs. We also investigated AQFP cells with different designs of flux trapping moats in the superconducting ground plane as well as compact AQFP cells that took advantage of the smaller feature sizes available in the new fabrication process, SFQ5ee+, at MIT Lincoln Laboratory. This new process features nine planarized Nb layers with a 0.25 $μ$m minimum linewidth. The fabricated circuits were tested in a liquid He probe and in a closed-cycle cryocooler using a controlled cooling rate through the superconducting critical temperature. Using multiple thermal cycles, we investigated flux trapping in the dense AQFP shift registers as well as in the registers using the old (sparse) AQFP designs at two levels of the residual magnetic field, about 0.53 $μ$T and about 1.2 $μ$T. The sparse designs demonstrated 95% to almost 100% probability of operation after the cooldown and very wide operation margins, although the flux trapping probability was increasing with circuit complexities. The margins were similarly wide in the newer dense designs, but flux trapping probability that rendered the registers nonoperational was significantly, by an order of magnitude, higher in the denser circuits and was also very sensitive to the moats' shape and location. Our findings indicate that AQFP circuits are amendable to increasing the scale of integration and further densification, but a careful moat design and optimization are required to reduce flux trapping effects in the dense AQFP circuits.

cond-mat.supr-con↗

arXiv2023

Development of Self-Shunted Josephson Junctions For a Ten-Superconductor-Layer Fabrication Process: Nb/NbN$_x$/Nb Junctions

To increase integration scale of superconductor electronics, we are developing a new, SFQ7ee, node of the fabrication process at MIT Lincoln Laboratory. In comparison to the existing SFQ5ee node, we increased the number of fully planarized superconducting layers to ten and utilized NbN and NbN/Nb kinetic inductors to increase the inductor number density above 100 million per cm$^2$. Increasing the Josephson junction (JJ) number density to the same level requires implementing self-shunted high-$J_c$ JJs. We investigated properties of Nb/NbN$_x$/Nb trilayer JJs as a potential replacement of high-$J_c$ Nb/Al-AlO$_x$/Nb JJs, where NbN$_x$ is a disordered, nonsuperconducting nitride deposited by reactive sputtering. Dependences of the $I_cR_n$ product and Josephson critical current density, $J_c$ on the NbN$_x$ barrier thickness and on temperature were studied in the thickness range from 5 nm to 20 nm. The fabricated JJs can be described by the microscopic theory of SNS junctions, assuming no suppression of the energy gap in Nb electrodes near the NbN$_x$ interfaces and a Cooper pair decay length in the NbN$_x$ barrier of about 2.3 nm. Current-voltage characteristics of the JJs are well described by the RCSJ model. In the studied range $J_c$ < 10 mA/$μ$$m^2$, the Nb/NbN$_x$/Nb JJs have lower specific resistance $R_nA$, lower $I_cR_n$ product, and a stronger dependence of the $I_cR_n$ on temperature than self-shunted or critically damped externally shunted Nb/Al-AlO$_x$/Nb JJs with the same critical current density; here $A$ is the JJ area, $R_n$ the JJ effective shunting resistance.

cond-mat.supr-con↗

arXiv2023

BioSFQ circuit family for neuromorphic computing: Bridging digital and analog domains of superconductor technologies

Superconductor single flux quantum (SFQ) technology is attractive for neuromorphic computing due to low energy dissipation and high, potentially up to 100 GHz, clock rates. We have recently suggested a new family of bioSFQ circuits (V.K. Semenov et al., IEEE TAS, vol. 32, no. 4, 1400105, 2022) where information is stored as a value of current in a superconducting loop and transferred as a rate of SFQ pulses propagating between the loops. This approach, in the simplest case dealing with positive numbers, requires single-line transfer channels. In the more general case of bipolar numbers, it requires dual-rail transfer channels. To address this need, we have developed a new comparator with a dual-rail output. This comparator is an essential part of a bipolar multiplier that has been designed, fabricated, and tested. We discuss bioSFQ circuits for implementing an analog bipolar divide operation $Y/X$ and a square root operation $X^{1/2}$. We discuss strategic advantages of the suggested bioSFQ approach, e.g., an inherently asynchronous character of bioSFQ cells which do not require explicit clock signals. As a result, bioSFQ circuits are free of racing errors and tolerant to occasional collision of propagating SFQ pulses. This tolerance is due to stochastic nature of data signals generated by comparators operating within their gray zone. The circuits were fabricated in the eight-niobium-layer fabrication process SFQ5ee developed for superconductor electronics at MIT Lincoln Laboratory.

cond-mat.supr-con↗

arXiv2023

Progress toward superconductor electronics fabrication process with planarized NbN and NbN/Nb layers

To increase density of superconductor digital and neuromorphic circuits by 10x and reach integration scale of $10^8$ Josephson junctions (JJs) per chip, we developed a new fabrication process on 200-mm wafers, using self-shunted Nb/Al-AlOx/Nb JJs and kinetic inductors. The process has a layer of JJs, a layer of resistors, and 10 fully planarized superconducting layers: 8 Nb layers and 2 layers of high kinetic inductance materials, Mo$_2$N and NbN, with sheet inductance of 8 pH/sq and 3 pH/sq, respectively. NbN films were deposited by two methods: with $T_c$=15.5 K by reactive sputtering of a Nb target in Ar+N$_2$ mixture; with $T_c$ in the range from 9 K to 13 K by plasma-enhanced chemical vapor deposition (PECVD) using Tris(diethylamido)(tert-butylimido)niobium(V) metalorganic precursor. PECVD of NbN was investigated to obtain conformal deposition and filling narrow trenches and vias with high depth-to-width ratios, which was not possible to achieve using sputtering and other physical vapor deposition (PVD) methods at temperatures below $200 ^oC$ required to prevent degradation of Nb/Al-AlOx/Nb junctions. Nb layers with 200 nm thickness are used in the process layer stack as ground planes to maintain a high level of interlayer shielding and low intralayer mutual coupling, for passive transmission lines with wave impedances matching impedances of JJs, typically <=50 $Ω$, and for low-value inductors. NbN and NbN/Nb bilayer are used for cell inductors. Using NbN/Nb bilayers and individual pattering of both layers to form inductors allowed us to minimize parasitic kinetic inductance associated with interlayer vias and connections to JJs as well as to increase critical currents of the vias. Fabrication details and results of electrical characterization of NbN films, wires, and vias, and comparison with Nb properties are given.

cond-mat.supr-con↗

arXiv2023

Self- and Mutual Inductance of NbN and Bilayer NbN/Nb Inductors in Planarized Fabrication Process With Nb Ground Planes

We present measurements of the self- and mutual inductance of NbN and bilayer NbN/Nb inductors with Nb ground plane(s) fabricated in an advanced process for superconductor electronics developed at MIT Lincoln Laboratory. In this process, the signal traces of logic cell inductors are made either of a 200-nm NbN layer with $T_c$=15 K or of an in-situ deposited NbN/Nb bilayer, replacing a 200-nm Nb layer M6 in the standard SFQ5ee process with nine superconducting layers. Nb ground planes were preserved to maintain a high level of interlayer shielding and low intralayer mutual coupling. A two-step patterning of the top Nb and the bottom NbN layers of the NbN/Nb bilayer allows to create inductors in a very wide range of linear inductance values, from low values ~ 0.4 pH/$μ$m typical for Nb geometrical inductors to ~ 35 pH/$μ$m typical to thin-film kinetic inductors. Mutual inductance of NbN and Nb inductors, of NbN inductors, and of bilayer inductors is the same as between two Nb inductors with the same geometry and placement between the ground planes, i.e., mutual inductance does not depend on superconducting properties of the signal traces in the studied range of linewidths. We measured magnetic field penetration depth and kinetic inductance of NbN films with thickness t=200 nm to be $λ$ = 491+/-5 nm and 1.51 pH/sq, and 2.06 pH/sq at t=150 nm. The kinetic inductance was found to be larger than that expected for superconductors with short mean free path, indicating a reduction in the superfluid density, likely due to carrier localization effects. Kinetic inductance associated with right-angled bends of the NbN inductors is negligible at linewidths $w<λ^2/t$, indicating a very small current crowding in structures with superconducting ground plane(s). Implementation of NbN and NbN/Nb inductors can significantly increase integration scale of superconductor digital electronics.

cond-mat.supr-con↗

arXiv2021

A new family of bioSFQ logic/memory cells

Superconductor electronics (SCE) is competing to become a platform for efficient implementations of neuromorphic computing and deep learning algorithms (DLAs) with projects mostly concentrating on searching for gates that would better mimic behavior of real neurons. In contrast, we believe that most of the required components have already been demonstrated during the long history of SCE, whereas the missing part is how to organize these components to efficiently implement DLAs. We propose a family of logic/memory cells in which stored multi-bit data are encoded by quasi-analog currents or magnetic flux in superconductor loops while transmitted data are encoded as the rate of SFQ pulses. We designed, fabricated, and tested some of the basic cells to demonstrate a proof of concept, e.g., a unipolar and bipolar multipliers based on Josephson junction comparators. We coined the term bioSFQ to clearly connote close but distinguishable relations between the conventional SFQ electronics and its new neuromorphic paradigm.

cond-mat.supr-con↗

arXiv2021

Mutual and self-inductance in planarized multilayered superconductor integrated circuits: Microstrips, striplines, bends, meanders, ground plane perforations

Data are presented on mutual and self-inductance of various inductors used in multilayered superconductor integrated circuits: microstrips and striplines with widths of signal traces from 250 nm to a few micrometers, located on the same circuit layer at various distances from each other (from 250 nm to a few micrometers) and/or on different layers spaced vertically; effect of long slits in the ground plane(s) along the inductors on their mutual inductance; inductance of right-angled bends; inductance of meanders. Simple analytical expressions for mutual and self-inductance of the basic inductors are given, describing experimental data with accuracy better than 2% in a very wide range of parameters. They can be used for superconductor integrated circuit design and calibration of numerical inductance extractors. Measurements were done using circuits fabricated in fully planarized fabrication processes with eight niobium layers and Nb/Al-AlOx/Nb Josephson junctions, known as the SFQ5ee and SC1 processes developed at MIT Lincoln Laboratory for superconductor electronics. Mutual inductance decreases exponentially with distance between striplines and as a second power of the distance between microstrips, strongly depends on magnetic field penetration depths in superconducting ground planes, whereas superconducting properties of the signal traces are practically immaterial. Weak dependence of mutual inductance on the linewidth of superconducting wires indicates that area of superconducting flux transformers - the essential component of all digital circuits using ac power, superconducting qubits, and sensor arrays - scales poorly with the linewidth, putting a predictable upper limit on the integration scale of such circuits.

cond-mat.supr-con↗

arXiv2021

SFQ bias for SFQ digital circuits

Superconductor electronics fabrication technology developed at MIT Lincoln Laboratory enables the development of VLSI digital circuits with millions of Josephson junctions per square centimeter. However, conventional DC and multi-phase AC biasing techniques already encounter serious challenges for scaling circuits above several hundred thousand junctions. In this work, we propose a novel AC-based biasing scheme for RSFQ-type logic families requiring DC bias. The major step toward this scheme is a superconducting AC/DC rectifier which we introduced at ASC 2014. Initially, we proposed to connect the rectifiers to 'payload cells' via superconducting inductors with large inductance in order to reduce parasitic effects of flux quantization. Recently, we discovered that this powering scheme works even better at a much lower value of the inductance, when it is just sufficient to hold only one or two flux quanta in the inductive loop between the converter and the payload. In this case, flux quantization in the loop becomes beneficial because the value of current fed into the payload is defined by the value of the coupling inductance. Therefore, our AC/SFQ converter powers the payload cell by a single flux quantum rather than by DC current. Such mode of operation is extremely energy efficient because the energy is used only to recover flux quantum consumed by the cell during the logic operation. We present designs of AC/SFQ converters comprising an AC/DC rectifier and a current conditioning circuit which we termed an SFQ filter. We also present test results and demonstrate AC/SFQ powering a payload circuit using circuits fabricated in a new, 150-nm node of Lincoln Laboratory fabrication technology using self-shunted Nb/AlOx-Al/Nb Josephson junctions with 600 $μ$A/$μ$$m^2$ critical current density and 200 nm minimum linewidth of inductors.

cond-mat.supr-con↗

arXiv2021

Inductance and mutual inductance of superconductor integrated circuit features with sizes down to 120 nm. Part I

Data are presented on inductance of various features used in superconductor digital integrated circuits such as microstrip and stripline inductors with linewidths down to 120 nm and different combinations of ground plane layers, effect of perforations of various sizes in the ground planes and their distance to the inductors on inductance, inductance of vias of various sizes between adjacent layers and composite vias between distant superconducting layers. Effects of magnetic flux trapping in ground plane moats on coupling to nearby inductors are discussed for circuit cooling in a residual field of several configurations. Test circuits used for the measurements were fabricated in a new 150-nm node of a fully planarized process with eight niobium layers, SC2 process, developed at MIT Lincoln Laboratory for superconductor electronics and in its 250-nm node SC1, as well as in the standard fabrication process SFQ5ee. The SC2 process utilizes 193-nm photolithography in combination with plasma etching and chemical mechanical planarization of interlayer dielectrics to define inductors with linewidth down to about 100 nm on critical layers. All other processes use 248 nm photolithography. Effects of variation of process parameters on circuit inductors are discussed. The measured data are compared with the results of inductance extraction using software packages InductEx and wxLC. Part II is devoted to mutual inductance of various closely spaced features in integrated circuits, meanders, and transformers.

cond-mat.supr-con↗

arXiv2020

Solid-state qubits integrated with superconducting through-silicon vias

As superconducting qubit circuits become more complex, addressing a large array of qubits becomes a challenging engineering problem. Dense arrays of qubits benefit from, and may require, access via the third dimension to alleviate interconnect crowding. Through-silicon vias (TSVs) represent a promising approach to three-dimensional (3D) integration in superconducting qubit arrays -- provided they are compact enough to support densely-packed qubit systems without compromising qubit performance or low-loss signal and control routing. In this work, we demonstrate the integration of superconducting, high-aspect ratio TSVs -- 10 $μ$m wide by 20 $μ$m long by 200 $μ$m deep -- with superconducting qubits. We utilize TSVs for baseband control and high-fidelity microwave readout of qubits using a two-chip, bump-bonded architecture. We also validate the fabrication of qubits directly upon the surface of a TSV-integrated chip. These key 3D integration milestones pave the way for the control and readout of high-density superconducting qubit arrays using superconducting TSVs.

quant-ph↗