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Evan McKinney

Publications and source records attributed to Evan McKinney.

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Fidelity-Aware Frequency Allocation and Transpilation Co-Design for Tunable Coupler Quantum Systems

Frequency crowding is a fundamental limitation in superconducting quantum architectures, particularly in tunable-coupler systems. We present a framework that explicitly models both coherent spectator-induced errors and incoherent lifetime effects through an error budgeting approach. Using this model, we analyze how frequency crowding impacts gate fidelity as module size and connectivity scale, and formulate a constrained optimization problem to assign qubit and coupler frequencies under realistic separation and hardware constraints. We demonstrate scalable frequency allocation strategies that minimize spectator-induced errors. We further show that increasing qubit count and coupling density within a module leads to a fidelity-connectivity tradeoff. To explore the benefits at the system scale, we have developed a noise-aware transpilation approach called FINESSE, which minimizes error by selecting high-fidelity paths that satisfy connectivity via SWAP insertion while jointly optimizing downstream gate execution. We demonstrate this physics-informed architecture-transpilation co-design approach for a SNAIL-based third-order coupler that natively realizes the $\sqrt{iSWAP}$ basis with frequency aware gate fidelities. On SNAIL architectures, FINESSE achieves an average 8.9% reduction in log-infidelity cost and 6.8% reduction in circuit depth vs. SABRE. We also compare results on IBM Brisbane's architecture.

quant-ph

Efficient Routing of Quantum LDPC Codes on Programmable 2D Toric Architectures

Quantum low-density parity-check codes are promising candidates towards scalable fault-tolerant quantum computation. Among these, bivariate bicycle (BB) codes offer superior encoding rates and large code distance compared to surface codes. However, their requirement on long-range stabilizer measurements poses significant challenges for implementation on realistic hardware with limited connectivity, such as superconducting circuit platforms. In this work, we introduce a novel hardware-software co-design that leverages a programmable communication network architecture to address these limitations. Our approach utilizes a 2D toric network of oscillators as a flexible communication fabric linking qubits at each site. Such architecture significantly reduces the number of long-range couplers required from $O(n)$ to $O(\sqrt{n})$. Dual-rail qubits, along with native gates including Swap-Wait-Swap gates and beamsplitter SWAPs, ensure that long-range two-qubit gates can be executed with high fidelity and low latency. To further enhance performance, our qubit layout and routing algorithm utilize symmetries of the codes and enable maximum parallelism for long-range two-qubit gates, maintaining a low syndrome extraction cycle duration and scalability over the code length. We perform circuit-level simulation with realistic noise modeling based on experimental hardware parameters, observing an logical error rate per logical qubit per cycle of 3.06\% for $[[18, 4, 4]]$ BB code, 2.6$\times$ less than the existing experimental result. These findings provide a practical roadmap and identify key technological advancements needed to achieve low-overhead fault-tolerant quantum computing at scale.

quant-ph

Symbolic Hamiltonian Compiler for Hybrid Qubit-Boson Processors

Quantum simulation of the interactions of fermions and bosons -- the fundamental particles of nature -- is essential for modeling complex quantum systems in material science, chemistry and high-energy physics and has been proposed as a promising application of fermion-boson quantum computers, which overcome the overhead encountered in mapping fermions and bosons to qubits. However, compiling the simulation of specific fermion-boson Hamiltonians into the natively available fermion-boson gate set is challenging. In particular, the large local dimension of bosons renders matrix-based compilation methods, as used for qubits and in existing tools such as Bosonic Qiskit or OpenFermion, challenging. We overcome this issue by introducing a novel symbolic compiler based on matrix-free symbolic manipulation of second quantised Hamiltonians, which automates the decomposition of fermion-boson second quantized problems into qubit-boson instruction set architectures. This integration establishes a comprehensive pipeline for simulating quantum systems on emerging qubit-boson and fermion-boson hardware, paving the way for their large-scale usage.

quant-ph

Autoregressive pairwise Graphical Models efficiently find ground state representations of stoquastic Hamiltonians

We introduce Autoregressive Graphical Models (AGMs) as an Ansatz for modeling the ground states of stoquastic Hamiltonians. Exact learning of these models for smaller systems show the dominance of the pairwise terms in the autoregressive decomposition, which informs our modeling choices when the Ansatz is used to find representations for ground states of larger systems. We find that simple AGMs with pairwise energy functions trained using first-order stochastic gradient methods often outperform more complex non-linear models trained using the more expensive stochastic reconfiguration method. We also test our models on Hamiltonians with frustration and observe that the simpler linear model used here shows faster convergence to the variational minimum in a resource-limited setting.

quant-ph

GULPS: Two-Qubit Gate Synthesis via Linear Programming for Heterogeneous Instruction Sets

Modern quantum hardware exposes heterogeneous two-qubit instruction sets through fractional, continuously parameterized, and per-pair native gates, but synthesis remains largely framed around CNOT and a small catalog of closed-form rules. We present \textbf{GULPS} (Global Unitary Linear Programming Synthesis), a two-qubit compiler that partitions synthesis into depth-$2$ segments and uses a linear program over quantum Littlewood--Richardson reachability inequalities to plant the intermediate invariants between them. Each segment becomes an independent low-dimensional least-squares fit, solved by a Gauss--Newton/Levenberg--Marquardt routine. On Haar-random two-qubit targets, GULPS is more than $500{\times}$ faster than the general-purpose synthesizers BQSKit and NuOp at strictly lower circuit cost. Against Qiskit's specialized \texttt{XXDecomposer} on $XX$-family ISAs, GULPS produces identical output circuits $3.9$--$9.2{\times}$ faster, compounding to $7$--$19{\times}$ on full-circuit transpilation. All decompositions reach the double-precision unitary-infidelity floor. As a byproduct, the continuous formulation yields a Haar-averaged lower bound on expected circuit cost, against which discrete calibration choices can be benchmarked. GULPS is distributed on PyPI and registers as a Qiskit translation-stage plugin.

quant-ph

Kernpiler: Compiler Optimization for Quantum Hamiltonian Simulation with Partial Trotterization

Quantum computing promises transformative impacts in simulating Hamiltonian dynamics, essential for studying physical systems inaccessible by classical computing. However, existing compilation techniques for Hamiltonian simulation, in particular the commonly used Trotter formulas struggle to provide gate counts feasible on current quantum computers for beyond-classical simulations. We propose partial Trotterization, where sets of non-commuting Hamiltonian terms are directly compiled allowing for less error per Trotter step and therefore a reduction of Trotter steps overall. Furthermore, a suite of novel optimizations are introduced which complement the new partial Trotterization technique, including reinforcement learning for complex unitary decompositions and high level Hamiltonian analysis for unitary reduction. We demonstrate with numerical simulations across spin and fermionic Hamiltonians that compared to state of the art methods such as Qiskit's Rustiq and Qiskit's Paulievolutiongate, our novel compiler presents up to 10x gate and depth count reductions.

quant-ph

Spectator-Aware Frequency Allocation in Tunable-Coupler Quantum Architectures

This paper addresses frequency crowding in SNAIL-based superconducting quantum modules. First, we present design constraints by describing a physical model for realizable gates within a module, and building a fidelity model using error budgeting derived from device characteristics. Second, we tackle the allocation problem by analyzing the impact of frequency crowding on gate fidelity as the radix of the module increases. We explore whether the heuristic gate fidelity can be optimized with a discrete set of qubit frequencies while adhering to defined separation thresholds. By leveraging a combination of analytical and numerical techniques, we demonstrate scalable frequency allocation strategies that minimize spectator-induced errors. Our results further indicate that removing edges leads to improved gate fidelities while maintaining sufficient connectivity, suggesting that edge density is not a limiting factor for NISQ-scale benchmarks. The findings have implications for designing robust, high-fidelity quantum systems with practical constraints on hardware and connectivity.

quant-ph

Towards Error Correction for Computing in Racetrack Memory

Computing-in-memory (CIM) promises to alleviate the Von Neumann bottleneck and accelerate data-intensive applications. Depending on the underlying technology and configuration, CIM enables implementing compute primitives in place, such as multiplication, search operations, and bulk bitwise logic operations. Emerging nonvolatile memory technologies such as spintronic Racetrack memory (RTM) promise not only unprecedented density but also significant parallelism through CIM. However, most CIM designs, including those based on RTM, exhibit high fault rates. Existing error correction codes (ECC) are not homomorphic over bitwise operations such as AND and OR, and hence cannot protect against CIM faults. This paper proposes CIRM-ECC, a technique to protect spintronic RTMs against CIM faults. At the core of CIRM-ECC, we use a recently proposed RTM-based CIM approach and leverage its peripheral circuitry to our implement our novel ECC codes. We show that CIRM-ECC can be applied to single-bit Hamming codes as well as multi-bit BCH codes.

cs.AR

MIRAGE: Quantum Circuit Decomposition and Routing Collaborative Design using Mirror Gates

Building efficient large-scale quantum computers is a significant challenge due to limited qubit connectivities and noisy hardware operations. Transpilation is critical to ensure that quantum gates are on physically linked qubits, while minimizing $\texttt{SWAP}$ gates and simultaneously finding efficient decomposition into native $\textit{basis gates}$. The goal of this multifaceted optimization step is typically to minimize circuit depth and to achieve the best possible execution fidelity. In this work, we propose $\textit{MIRAGE}$, a collaborative design and transpilation approach to minimize $\texttt{SWAP}$ gates while improving decomposition using $\textit{mirror gates}$. Mirror gates utilize the same underlying physical interactions, but when their outputs are reversed, they realize a different or $\textit{mirrored}$ quantum operation. Given the recent attention to $\sqrt{\texttt{iSWAP}}$ as a powerful basis gate with decomposition advantages over $\texttt{CNOT}$, we show how systems that implement the $\texttt{iSWAP}$ family of gates can benefit from mirror gates. Further, $\textit{MIRAGE}$ uses mirror gates to reduce routing pressure and reduce true circuit depth instead of just minimizing $\texttt{SWAP}$s. We explore the benefits of decomposition for $\sqrt{\texttt{iSWAP}}$ and $\sqrt[4]{\texttt{iSWAP}}$ using mirror gates, including both expanding Haar coverage and conducting a detailed fault rate analysis trading off circuit depth against approximate gate decomposition. We also describe a novel greedy approach accepting mirror substitution at different aggression levels within MIRAGE. Finally, for $\texttt{iSWAP}$ systems that use square-lattice topologies, $\textit{MIRAGE}$ provides an average of 29.6% reduction in circuit depth by eliminating an average of 59.9f% $\texttt{SWAP}$ gates, which ultimately improves the practical applicability of our algorithm.

quant-ph

Parallel Driving for Fast Quantum Computing Under Speed Limits

Increasing quantum circuit fidelity requires an efficient instruction set to avoid errors from decoherence. The choice of a two-qubit (2Q) hardware basis gate depends on a quantum modulator's native Hamiltonian interactions and applied control drives. In this paper, we propose a collaborative design approach to select the best ratio of drive parameters that determine the best basis gate for a particular modulator. This requires considering the theoretical computing power of the gate along with the practical speed limit of that gate, given the modulator drive parameters. The practical speed limit arises from the couplers' tolerance for strong driving when one or more pumps is applied, for which some combinations can result in higher overall speed limits than others. Moreover, as this 2Q basis gate is typically applied multiple times in succession, interleaved by 1Q gates applied directly to the qubits, the speed of the 1Q gates can become a limiting factor for the quantum circuit. We propose a parallel-drive approach that drives the modulator and qubits simultaneously, allowing a richer capability of the 2Q basis gate and in some cases for this 1Q drive time to be absorbed entirely into the 2Q operation. This allows increasingly short duration 2Q gates while mitigating a significant source of overhead in some quantum systems. On average, this approach can decrease circuit duration by 17.84% and decrease infidelity for random 2Q gates by 10.5% compared to the best basic 2Q gate, $\sqrt{\texttt{iSWAP}}$.

quant-ph

Co-Designed Architectures for Modular Superconducting Quantum Computers

Noisy, Intermediate Scale Quantum (NISQ) computers have reached the point where they can show the potential for quantum advantage over classical computing. Unfortunately, NISQ machines introduce sufficient noise that even for moderate size quantum circuits the results can be unreliable. We propose a co-designed superconducting quantum computer using a Superconducting Nonlinear Asymmetric Inductive eLement (SNAIL) modulator. The SNAIL modulator is designed by considering both the ideal fundamental qubit gate operation while maximizing the qubit coupling capabilities. First, the SNAIL natively implements $\sqrt[n]{\texttt{iSWAP}}$ gates realized through proportionally scaled pulse lengths. This naturally includes $\sqrt{\texttt{iSWAP}}$, which provides an advantage over $\texttt{CNOT}$ as a basis gate. Second, the SNAIL enables high-degree couplings that allow rich and highly parallel qubit connection topologies without suffering from frequency crowding. Building on our previously demonstrated SNAIL-based quantum state router we propose a quantum 4-ary tree and a hypercube inspired corral built from interconnected quantum modules. We compare their advantage in data movement based on necessary \texttt{SWAP} gates to the traditional lattice and heavy-hex lattice used in latest commercial quantum computers. We demonstrate the co-design advantage of our SNAIL-based machine with $\sqrt{\texttt{iSWAP}}$ basis gates and rich topologies against $\texttt{CNOT}$/heavy-hex and $\texttt{FSIM}$/lattice for 16-20 qubit and extrapolated designs circa 80 qubit architectures. We compare total circuit time and total gate count to understand fidelity for systems dominated by decoherence and control imperfections, respectively. Finally, we provide a gate duration sensitivity study on further decreasing the SNAIL pulse length to realize $\sqrt[n]{\texttt{iSWAP}}$ qubit systems to reduce decoherence times.

quant-ph