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Fabian Magerl

Publications and source records attributed to Fabian Magerl.

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Stretch-free, shape-induced 3D Island-Bridge Networks for flexible TFTs on Silicon Planar Technology verified through Bending and Scalability to 9x9 Matrix

This study presents a CMOS-compatible, fully integrated three-dimensional island-bridge concept for flexible electronics on silicon planar technology. By embedding metal bridges within trenches in a polyimide-passivated island matrix, the approach localizes mechanical stress to the bridges whereby active components on the islands are protected from mechanical stress, enabling high-performance thin-film transistors (TFTs) on flexible substrates. A concave, arc-shape forming fill in trenches between the islands and backside etching yield freestanding 3D bridges. Numerical simulations to determine the minimum bending radius reveal a characteristic stress distribution in the bridges during bending, with peak stresses at the bridge-island transitions. Variation of trench depth modulates von Mises stress, identifying design parameters for reliability. Experimental validation demonstrates TFT operation under bending, with stable threshold voltage, subthreshold swing, and saturation mobility across a range of bending radii; broader bridges exhibit enhanced mechanical robustness. A 9x9 island-bridge matrix with addressable integration of TFTs across islands demonstrates the scalability of the concept. Overall, the results verify the manufacturability of stretch-free 3D metal bridges where the three-dimensional shape is defined by the topography of the concave trench filling, with integrated active devices, and confirm the mechanical and electrical functionality of the produced flexible substrates.

physics.app-ph

Impact of Surface Treatment on Noise in PL-Measurements of Silicon Vacancies in 4H-SiC Lateral pin-Diodes

Silicon vacancies ($V_\mathrm{Si}$) in 4H-SiC are promising candidates for quantum technologies due to their long spin coherence times and integrability into mature semiconductor platforms. However, conventional CMOS-compatible processing introduces significant photoluminescence noise from passivation layers and crystal damage, degrading color center coherence and excitation linewidths. This work evaluates strategies to minimize such background noise. Thermally grown oxides with nitrogen monoxide annealing provide excellent low-noise passivation, remaining stable during subsequent $600\,^{\circ}\mathrm{C}$ thermal treatments. Furthermore, combining reactive ion etching with atomic layer etching eliminates ion-induced surface damage. Into lateral pin-diodes, used for stark shift and photoluminescent excitation linewidth tuning, a selectively etched optical window is integrated. These devices show ideal electrical properties -- blocking up to $150\,\mathrm{V}$ with leakage current below $10\,\mathrm{pA}/\mu\mathrm{m}$ -- while significantly enhancing the $V_\mathrm{Si}$ environment. Single emitters in these pin-diodes show an increased signal-to-noise ratio of 15 for near-surface and of 50 for deeper emitters on both c-plane and a-plane wafers.

quant-ph