arXiv subjects

Fahd A. Mohiyaddin

Publications and source records attributed to Fahd A. Mohiyaddin.

At least 19 recordsLinked to original sources

arXiv2026

Driving Exchange Interaction in Spin Qubits with Quasi-Zero Pulses

The implementation of high-fidelity quantum gates for spin qubits requires accurate control of exchange interactions between electrons confined in quantum dots, but pulse distortions can limit this control accuracy. Although linear-dynamical distortions can be compensated for by appropriately convolving the control signal, determining the necessary convolution requires detailed knowledge of the distortion's transfer function, and therefore the calibration of numerous parameters. Alternatively, control pulses can be designed to have a net-zero time integral canceling out linear-dynamical pulse distortions. We generalize net-zero pulse designs to quasi-zero pulses allowing net-positive but reduced time integrals. Using these pulse designs, we systematically develop complete gate sets for exchange-only qubits, and study the resulting tradeoffs between pulse duration, fidelity, and the required number of tunable parameters, both in simulation and experiment. We benchmark the optimized gate pulses on Intel's Tunnel Falls six-dot device and show they achieve fidelities similar to those obtained with a full filtering approach, with identical pulse durations and fewer tuning parameters. This reduction in complexity opens the door to fast and easily automated calibration schemes compatible with large-scale commercial quantum devices.

quant-ph↗

arXiv2026

Valley Splitting Correlations Across a Silicon Quantum Well Containing Germanium

Quantum dots in SiGe/Si/SiGe heterostructures host coherent electron spin qubits, which are promising for future quantum computers. The silicon quantum well hosts near-degenerate electron valley states, creating a low-lying excited state that is known to reduce spin qubit readout and control fidelity. The valley energy splitting is dominated by the microscopic disorder in the SiGe alloy and at the Si/SiGe interfaces, and while Si devices are compatible with large-scale semiconductor manufacturing, achieving a uniformly large valley splitting energy across a many-qubit device spanning mesoscopic distances is an outstanding challenge. In this work we study valley splitting variations in a 1D quantum dot array, formed in a Si$_{0.972}$Ge$_{0.028}$ quantum well, manufactured by Intel. We observe correlations in valley splitting, at both sub-100nm (single gate) and >1$μ$m (device) lengthscales, that are consistent with alloy disorder-dominated theory and simulation. Our results develop the mesoscopic understanding of Si/SiGe heterostructures necessary for scalable device design.

cond-mat.mes-hall↗

arXiv2025

Operating two exchange-only qubits in parallel

Semiconductors are among the most promising platforms to implement large-scale quantum computers, as advanced manufacturing techniques allow fabrication of large quantum dot arrays. Various qubit encodings can be used to store and manipulate quantum information on these quantum dot arrays. Regardless of qubit encoding, precise control over the exchange interaction between electrons confined in quantum dots in the array is critical. Furthermore, it is necessary to execute high-fidelity quantum operations concurrently to make full use of the limited coherence of individual qubits. Here, we demonstrate the parallel operation of two exchange-only qubits, consisting of six quantum dots in a linear arrangement. Using randomized benchmarking techniques, we show that issuing pulses on the five barrier gates to modulate exchange interactions in a maximally parallel way maintains the quality of qubit control relative to sequential operation. The techniques developed to perform parallel exchange pulses can be readily adapted to other quantum-dot based encodings. Moreover, we show the first experimental demonstrations of an iSWAP gate and of a charge-locking Pauli spin blockade readout method. The results are validated using cross-entropy benchmarking, a technique useful for performance characterization of larger quantum computing systems; here it is used for the first time on a quantum system based on semiconductor technology.

quant-ph↗

arXiv2025

Fast quantum gates for exchange-only qubits using simultaneous exchange pulses

The benefit of exchange-only qubits compared to other spin qubit types is the universal control using only voltage controlled exchange interactions between neighboring spins. As a compromise, qubit operations have to be constructed from non-orthogonal rotation axes of the Bloch sphere and result in rather long pulsing sequences. This paper aims to develop a faster implementation of single-qubit gates using simultaneous exchange pulses and manifests their potential for the construction of two-qubit gates. We introduce pulse sequences in which single-qubit gates could be executed faster and show that subsequences on three spins in two-qubit gates could be implemented in fewer steps. Our findings can particularly speed up gate sequences for realistic idle times between sequential pulses and we show that this advantage increases with more interconnectivity of the quantum dots. We further demonstrate how a phase operation can introduce a relative phase between the computational and some of the leakage states, which can be advantageous for the construction of two-qubit gates. In addition to our theoretical analysis, we experimentally demonstrate and characterize a simultaneous exchange implementation of $X$ rotations in a SiGe quantum dot device and compare to the state of the art with sequential exchange pulses.

quant-ph↗

arXiv2025

Short two-qubit pulse sequences for exchange-only spin qubits in 2D layouts

Exchange-only (EO) spin qubits in quantum dots offer an expansive design landscape for architecting scalable device layouts. The study of two-EO-qubit operations, which involve six electrons in six quantum dots, has so far been limited to a small number of the possible configurations, and previous works lack analyses of design considerations and implications for quantum error correction. Using a simple and fast optimization method, we generate complete pulse sequences for CX, CZ, iSWAP, leakage-controlled CX, and leakage-controlled CZ two-qubit gates on 450 unique planar six-dot topologies and analyze differences in sequence length (up to 43\% reduction) across topology classes. In addition, we show that relaxing constraints on post-operation spin locations can yield further reductions in sequence length; conversely, constraining these locations in a particular way generates a CXSWAP operation with minimal additional cost over a standard CX. We integrate this pulse library into the Intel quantum stack and experimentally verify pulse sequences on a Tunnel Falls chip for different operations in a linear-connectivity device to confirm that they work as expected. Finally, we explore architectural implications of these results for quantum error correction. Our work guides hardware and software design choices for future implementations of scalable quantum dot architectures.

quant-ph↗

arXiv2024

12-spin-qubit arrays fabricated on a 300 mm semiconductor manufacturing line

Intels efforts to build a practical quantum computer are focused on developing a scalable spin-qubit platform leveraging industrial high-volume semiconductor manufacturing expertise and 300 mm fabrication infrastructure. Here, we provide an overview of the design, fabrication, and demonstration of a new customized quantum test chip, which contains 12-quantum-dot spin-qubit linear arrays, code named Tunnel Falls. These devices are fabricated using immersion and extreme ultraviolet lithography (EUV), along with other standard high-volume manufacturing (HVM) processes, as well as production-level process control. We present key device features and fabrication details, as well as qubit characterization results confirming device functionality. These results corroborate our fabrication methods and are a crucial step towards scaling of extensible 2D qubit array schemes.

cond-mat.mes-hall↗

arXiv2024

Probing single electrons across 300 mm spin qubit wafers

Building a fault-tolerant quantum computer will require vast numbers of physical qubits. For qubit technologies based on solid state electronic devices, integrating millions of qubits in a single processor will require device fabrication to reach a scale comparable to that of the modern CMOS industry. Equally importantly, the scale of cryogenic device testing must keep pace to enable efficient device screening and to improve statistical metrics like qubit yield and voltage variation. Spin qubits based on electrons in Si have shown impressive control fidelities but have historically been challenged by yield and process variation. Here we present a testing process using a cryogenic 300 mm wafer prober to collect high-volume data on the performance of hundreds of industry-manufactured spin qubit devices at 1.6 K. This testing method provides fast feedback to enable optimization of the CMOS-compatible fabrication process, leading to high yield and low process variation. Using this system, we automate measurements of the operating point of spin qubits and probe the transitions of single electrons across full wafers. We analyze the random variation in single-electron operating voltages and find that the optimized fabrication process leads to low levels of disorder at the 300 mm scale. Together these results demonstrate the advances that can be achieved through the application of CMOS industry techniques to the fabrication and measurement of spin qubit devices.

quant-ph↗

arXiv2023

Modelling semiconductor spin qubits and their charge noise environment for quantum gate fidelity estimation

The spin of an electron confined in semiconductor quantum dots is currently a promising candidate for quantum bit (qubit) implementations. Taking advantage of existing CMOS integration technologies, such devices can offer a platform for large scale quantum computation. However, a quantum mechanical framework bridging a device's physical design and operational parameters to the qubit energy space is lacking. Furthermore, the spin to charge coupling introduced by intrinsic or induced Spin-Orbit-Interaction (SOI) exposes the qubits to charge noise compromising their coherence properties and inducing quantum gate errors. We present here a co-modelling framework for double quantum dot (DQD) devices and their charge noise environment. We use a combination of an electrostatic potential solver, full configuration interaction quantum mechanical methods and two-level-fluctuator models to study the quantum gate performance in realistic device designs and operation conditions. We utilize the developed models together alongside the single electron solutions of the quantum dots to simulate one- and two- qubit gates in the presence of charge noise. We find an inverse correlation between quantum gate errors and quantum dot confinement frequencies. We calculate X-gate fidelities >97% in the simulated Si-MOS devices at a typical TLF densities. We also find that exchange driven two-qubit SWAP gates show higher sensitivity to charge noise with fidelities down to 91% in the presence of the same density of TLFs. We further investigate the one- and two- qubit gate fidelities at different TLF densities. We find that given the small size of the quantum dots, sensitivity of a quantum gate to the distance between the noise sources and the quantum dot creates a strong variability in the quantum gate fidelities which can compromise the device yields in scaled qubit technologies.

cond-mat.mes-hall↗

arXiv2021

Millikelvin temperature cryo-CMOS multiplexer for scalable quantum device characterisation

Quantum computers based on solid state qubits have been a subject of rapid development in recent years. In current Noisy Intermediate-Scale Quantum (NISQ) technology, each quantum device is controlled and characterised though a dedicated signal line between room temperature and base temperature of a dilution refrigerator. This approach is not scalable and is currently limiting the development of large-scale quantum system integration and quantum device characterisation. Here we demonstrate a custom designed cryo-CMOS multiplexer operating at 32 mK. The multiplexer exhibits excellent microwave properties up to 10 GHz at room and millikelvin temperatures. We have increased the characterisation throughput with the multiplexer by measuring four high-quality factor superconducting resonators using a single input and output line in a dilution refrigerator. Our work lays the foundation for large-scale microwave quantum device characterisation and has the perspective to address the wiring problem of future large-scale quantum computers.

quant-ph↗

arXiv2021

High mobility SiMOSFETs fabricated in a full 300mm CMOS process

The quality of the semiconductor-barrier interface plays a pivotal role in the demonstration of high quality reproducible quantum dots for quantum information processing. In this work, we have measured SiMOSFET Hall bars on undoped Si substrates in order to investigate the quality of the devices fabricated in a full CMOS process. We report a record mobility of 17'500 cm2/Vs with a sub-10 nm oxide thickness indicating a high quality interface, suitable for future qubit applications. We also study the influence of gate materials on the mobilities and discuss the underlying mechanisms, giving insight into further material optimization for large scale quantum processors.

cond-mat.mes-hall↗

arXiv2020

Exchange coupling in a linear chain of three quantum-dot spin qubits in silicon

Quantum gates between spin qubits can be implemented leveraging the natural Heisenberg exchange interaction between two electrons in contact with each other. This interaction is controllable by electrically tailoring the overlap between electronic wavefunctions in quantum dot systems, as long as they occupy neighbouring dots. An alternative route is the exploration of superexchange - the coupling between remote spins mediated by a third idle electron that bridges the distance between quantum dots. We experimentally demonstrate direct exchange coupling and provide evidence for second neighbour mediated superexchange in a linear array of three single-electron spin qubits in silicon, inferred from the electron spin resonance frequency spectra. We confirm theoretically through atomistic modeling that the device geometry only allows for sizeable direct exchange coupling for neighbouring dots, while next nearest neighbour coupling cannot stem from the vanishingly small tail of the electronic wavefunction of the remote dots, and is only possible if mediated.

quant-ph↗

arXiv2018

Robust electric dipole transition at microwave frequencies for nuclear spin qubits in silicon

The nuclear spin state of a phosphorus donor ($^{31}$P) in isotopically enriched silicon-28 is an excellent host to store quantum information in the solid state. The spin's insensitivity to electric fields yields a solid-state qubit with record coherence times, but also renders coupling to other quantum systems very challenging. Here, we describe how to generate a strong electric dipole ($>100$ Debye) at microwave frequencies for the nuclear spin. This is achieved by applying a magnetic drive to the spin of the donor-bound electron, while simultaneously controlling its charge state with electric fields. Under certain conditions, the microwave magnetic drive also renders the nuclear spin resonance frequency and electric dipole strongly insensitive to electrical noise, yielding long ($>1$ ms) dephasing times and robust gate operations. The nuclear spin could then be strongly coupled to microwave resonators, with a vacuum Rabi splitting of order 1 MHz, or to other nuclear spins, nearly half a micrometer apart, via strong electric dipole-dipole interaction. This work brings the $^{31}$P nuclear qubit into the realm of hybrid quantum systems and opens up new avenues in quantum information processing.

cond-mat.mes-hall↗

arXiv2018

Quantum Computing Circuits and Devices

The development of quantum computing technologies builds on the unique features of quantum physics while borrowing familiar principles from the design of conventional devices. We introduce the fundamental concepts required for designing and operating quantum computing devices by reviewing state of the art efforts to fabricate and demonstrate quantum gates and qubits. We summarize the near-term challenges for devices based on semiconducting, superconducting, and trapped ion technologies with an emphasis on design tools as well as methods of verification and validation. We then discuss the generation and synthesis of quantum circuits for higher-order logic that can be carried out using quantum computing devices.

quant-ph↗

arXiv2017

Quantum Accelerators for High-Performance Computing Systems

We define some of the programming and system-level challenges facing the application of quantum processing to high-performance computing. Alongside barriers to physical integration, prominent differences in the execution of quantum and conventional programs challenges the intersection of these computational models. Following a brief overview of the state of the art, we discuss recent advances in programming and execution models for hybrid quantum-classical computing. We discuss a novel quantum-accelerator framework that uses specialized kernels to offload select workloads while integrating with existing computing infrastructure. We elaborate on the role of the host operating system to manage these unique accelerator resources, the prospects for deploying quantum modules, and the requirements placed on the language hierarchy connecting these different system components. We draw on recent advances in the modeling and simulation of quantum computing systems with the development of architectures for hybrid high-performance computing systems and the realization of software stacks for controlling quantum devices. Finally, we present simulation results that describe the expected system-level behavior of high-performance computing systems composed from compute nodes with quantum processing units. We describe performance for these hybrid systems in terms of time-to-solution, accuracy, and energy consumption, and we use simple application examples to estimate the performance advantage of quantum acceleration.

quant-ph↗

arXiv2017

Silicon quantum processor with robust long-distance qubit couplings

Practical quantum computers require the construction of a large network of highly coherent qubits, interconnected in a design robust against errors. Donor spins in silicon provide state-of-the-art coherence and quantum gate fidelities, in a physical platform adapted from industrial semiconductor processing. Here we present a scalable design for a silicon quantum processor that does not require precise donor placement and allows hundreds of nanometers inter-qubit distances, therefore facilitating fabrication using current technology. All qubit operations are performed via electrical means on the electron-nuclear spin states of a phosphorus donor. Single-qubit gates use low power electric drive at microwave frequencies, while fast two-qubit gates exploit electric dipole-dipole interactions. Microwave resonators allow for millimeter-distance entanglement and interfacing with photonic links. Sweet spots protect the qubits from charge noise up to second order, implying that all operations can be performed with error rates below quantum error correction thresholds, even without any active noise cancellation technique.

cond-mat.mes-hall↗

arXiv2016

A Computational Workflow for Designing Silicon Donor Qubits

Developing devices that can reliably and accurately demonstrate the principles of superposition and entanglement is an on-going challenge for the quantum computing community. Modeling and simulation offer attractive means of testing early device designs and establishing expectations for operational performance. However, the complex integrated material systems required by quantum device designs are not captured by any single existing computational modeling method. We examine the development and analysis of a multi-staged computational workflow that can be used to design and characterize silicon donor qubit systems with modeling and simulation. Our approach integrates quantum computational chemistry calculations with electrostatic field solvers to perform detailed simulations of a phosphorus dopant in silicon. We show how atomistic details can be synthesized into an operational model for the logical gates that define quantum computation in this particular technology. The resulting computational workflow realizes a design tool for silicon donor qubits that can help verify and validate current and near-term experimental devices.

quant-ph↗

arXiv2016

A Dressed Spin Qubit in Silicon

Coherent dressing of a quantum two-level system provides access to a new quantum system with improved properties - a different and easily tuneable level splitting, faster control, and longer coherence times. In our work we investigate the properties of the dressed, donor-bound electron spin in silicon, and probe its potential for the use as quantum bit in scalable architectures. The two dressed spin-polariton levels constitute a quantum bit that can be coherently driven with an oscillating magnetic field, an oscillating electric field, by frequency modulating the driving field, or by a simple detuning pulse. We measure coherence times of $T_{2ρ}^*=2.4$ ms and $T_{2ρ}^{\rm Hahn}=9$ ms, one order of magnitude longer than those of the undressed qubit. Furthermore, the use of the dressed states enables coherent coupling of the solid-state spins to electric fields and mechanical oscillations.

cond-mat.mes-hall↗

arXiv2016

Transport of Spin Qubits with Donor Chains under Realistic Experimental Conditions

The ability to transport quantum information across some distance can facilitate the design and operation of a quantum processor. One-dimensional spin chains provide a compact platform to realize scalable spin transport for a solid-state quantum computer. Here, we model odd-sized donor chains in silicon under a range of experimental non-idealities, including variability of donor position within the chain. We show that the tolerance against donor placement inaccuracies is greatly improved by operating the spin chain in a mode where the electrons are confined at the Si-SiO$_2$ interface. We then estimate the required timescales and exchange couplings, and the level of noise that can be tolerated to achieve high fidelity transport. We also propose a protocol to calibrate and initialize the chain, thereby providing a complete guideline for realizing a functional donor chain and utilizing it for spin transport.

cond-mat.mes-hall↗