arXiv subjects

Fangfei Liu

Publications and source records attributed to Fangfei Liu.

6 recordsLinked to original sources

arXiv2025

Performance of multiple filter-cavity schemes for frequency-dependent squeezing in gravitational-wave detectors

Gravitational-wave detectors use state-of-the-art quantum technologies to reduce the noise induced by vacuum fluctuations, via injection of squeezed states of light. Future detectors, such as Einstein Telescope, may require the use of two filter cavities or a 3-mirror coupled filter cavity to achieve a complex rotation of the squeezing ellipse, in order to reduce the quantum noise over the whole detector bandwidth. In this work, we compare the theoretical feasibility and performances of these two optical layouts and their resilience with respect to different degradation sources (optical losses, mismatching, locking precision), analytically and numerically. We extend previous analysis on squeezing degradation and find that the coupled cavity scheme provides similar or better performances than the two-cavity option, in terms of resilience with respect to imperfections and optical losses. We further highlight the role of mode-mismatch phases in limiting squeezing. Finally, we propose a possible two-step implementation scheme for Einstein Telescope using a single filter cavity that can be possibly upgraded into a coupled filter cavity.

gr-qc↗

arXiv2025

Beijing Normal University 12-meter Interferometric kHz GW Detector Prototype: Design and Scientific Prospects

Current gravitational-wave detectors have achieved remarkable sensitivity around 100 Hz, enabling ground-breaking discoveries. Enhancing sensitivity at higher frequencies in the kilohertz (kHz) range promises access to rich physics, particularly the extreme conditions during the merger stage of binary neutron stars. However, the high-frequency sensitivity of Michelson-based interferometers is fundamentally limited by their linear optical cavities, which are optimized for low-frequency signal enhancement. In [Phys. Rev. X 13, 021019 (2023)], a new configuration employing an L-shaped optical resonator was proposed to overcome this limitation, offering exceptional sensitivity in the kHz band. As a pathfinder, the 12-meter prototype at Beijing Normal University is designed to demonstrate the sensing and control schemes of this new kHz detector configuration and to explore its performance in the high-power regime with suspended optics. Beyond its primary scientific goal, the prototype also offers potential sensitivity in the megahertz (MHz) range, potentially enabling constraints on exotic sources. This paper presents an overview of the prototype, including its optical design and current development status of key components.

physics.optics↗

arXiv2022

Chameleon Cache: Approximating Fully Associative Caches with Random Replacement to Prevent Contention-Based Cache Attacks

Randomized, skewed caches (RSCs) such as CEASER-S have recently received much attention to defend against contention-based cache side channels. By randomizing and regularly changing the mapping(s) of addresses to cache sets, these techniques are designed to obfuscate the leakage of memory access patterns. However, new attack techniques, e.g., Prime+Prune+Probe, soon demonstrated the limits of RSCs as they allow attackers to more quickly learn which addresses contend in the cache and use this information to circumvent the randomization. To yet maintain side-channel resilience, RSCs must change the random mapping(s) more frequently with adverse effects on performance and implementation complexity. This work aims to make randomization-based approaches more robust to allow for reduced re-keying rates and presents Chameleon Cache. Chameleon Cache extends RSCs with a victim cache (VC) to decouple contention in the RSC from evictions observed by the user. The VC allows Chameleon Cache to make additional use of the multiple mappings RSCs provide to translate addresses to cache set indices: when a cache line is evicted from the RSC to the VC under one of its mappings, the VC automatically reinserts this evicted line back into the RSC by using a different mapping. As a result, the effects of previous RSC set contention are hidden and Chameleon Cache exhibits side-channel resistance and eviction patterns similar to fully associative caches with random replacement. We show that Chameleon Cache has performance overheads of < 1% and stress that VCs are more generically helpful to increase side-channel resistance and re-keying intervals of randomized caches.

cs.CR↗

arXiv2022

CacheFX: A Framework for Evaluating Cache Security

Over the last two decades, the danger of sharing resources between programs has been repeatedly highlighted. Multiple side-channel attacks, which seek to exploit shared components for leaking information, have been devised, mostly targeting shared caching components. In response, the research community has proposed multiple cache designs that aim at curbing the source of side channels. With multiple competing designs, there is a need for assessing the level of security against side-channel attacks that each design offers. In this work we propose CacheFX, a flexible framework for assessing and evaluating the resilience of cache designs to side-channel attacks. CacheFX allows the evaluator to implement various cache designs, victims, and attackers, as well as to exercise them for assessing the leakage of information via the cache. To demonstrate the power of CacheFX, we implement multiple cache designs and replacement algorithms, and devise three evaluation metrics that measure different aspects of the caches:(1) the entropy induced by a memory access; (2) the complexity of building an eviction set; and (3) protection against cryptographic attacks. Our experiments highlight that different security metrics give different insights to designs, making a comprehensive analysis mandatory. For instance, while eviction-set building was fastest for randomized skewed caches, these caches featured lower eviction entropy and higher practical attack complexity. Our experiments show that all non-partitioned designs allow for effective cryptographic attacks. However, in state-of-the-art secure caches, eviction-based attacks are more difficult to mount than occupancy-based attacks, highlighting the need to consider the latter in cache design.

cs.CR↗

arXiv2021

Speculative Interference Attacks: Breaking Invisible Speculation Schemes

Recent security vulnerabilities that target speculative execution (e.g., Spectre) present a significant challenge for processor design. The highly publicized vulnerability uses speculative execution to learn victim secrets by changing cache state. As a result, recent computer architecture research has focused on invisible speculation mechanisms that attempt to block changes in cache state due to speculative execution. Prior work has shown significant success in preventing Spectre and other vulnerabilities at modest performance costs. In this paper, we introduce speculative interference attacks, which show that prior invisible speculation mechanisms do not fully block these speculation-based attacks. We make two key observations. First, misspeculated younger instructions can change the timing of older, bound-to-retire instructions, including memory operations. Second, changing the timing of a memory operation can change the order of that memory operation relative to other memory operations, resulting in persistent changes to the cache state. Using these observations, we demonstrate (among other attack variants) that secret information accessed by mis-speculated instructions can change the order of bound-to-retire loads. Load timing changes can therefore leave secret-dependent changes in the cache, even in the presence of invisible speculation mechanisms. We show that this problem is not easy to fix: Speculative interference converts timing changes to persistent cache-state changes, and timing is typically ignored by many cache-based defenses. We develop a framework to understand the attack and demonstrate concrete proof-of-concept attacks against invisible speculation mechanisms. We provide security definitions sufficient to block speculative interference attacks; describe a simple defense mechanism with a high performance cost; and discuss how future research can improve its performance.

cs.AR↗

arXiv2016

Cloud Server Benchmarks for Performance Evaluation of New Hardware Architecture

Adding new hardware features to a cloud computing server requires testing both the functionalities and the performance of the new hardware mechanisms. However, commonly used cloud computing server workloads are not well-represented by the SPEC integer and floating-point benchmark and Parsec suites typically used by the computer architecture community. Existing cloud benchmark suites for scale-out or scale-up computing are not representative of the most common cloud usage, and are very difficult to run on a cycle-accurate simulator that can accurately model new hardware, like gem5. In this paper, we present PALMScloud, a suite of cloud computing benchmarks for performance evaluation of cloud servers, that is ready to run on the gem5 cycle-accurate simulator. We demonstrate how our cloud computing benchmarks are used in evaluating the cache performance of a new secure cache called Newcache as a case study. We hope that these cloud benchmarks, ready to run on a dual-machine gem5 simulator or on real machines, can be useful to other researchers interested in improving hardware micro-architecture and cloud server performance.

cs.DC↗