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Felix Hahn

Publications and source records attributed to Felix Hahn.

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SoK: From Silicon to Netlist and Beyond $-$ Two Decades of Hardware Reverse Engineering Research

Hardware serves as the root of trust in modern computing systems, making Hardware Reverse Engineering (HRE) essential for security assurance$-$from design verification and supply-chain integrity to vulnerability discovery. We scope HRE to netlist recovery and its subsequent analysis, spanning the three subdomains of Integrated Circuit (IC), Field-Programmable Gate Array (FPGA), and netlist reverse engineering. These subdomains differ in their methodologies, but share core processes and are shaped by common requirements and legal constraints of the same stakeholders. Despite an increasing number of publications, the field lacks a systematic understanding of how these obstacles have stunted the research ecosystem. To address this gap, we present the first large-scale Systematization of Knowledge (SoK) of the HRE workflow, analyzing 187 peer-reviewed publications. Across all three subdomains, we identify eleven concrete technical challenges$-$from a widening gap between academic research and modern semiconductor technology nodes to overly idealized assumptions in netlist analysis$-$and propose actionable directions for each. A retrospective evaluation of all 30 published artifacts reveals that key results could be reproduced for only seven, a mere 4 % of all 187 papers in our corpus, confirming a systemic reproducibility crisis. We trace both the technical and reproducibility challenges to three structural barriers that recur across all subdomains: scarce reusable artifacts, missing benchmarks, and unresolved legal constraints on data sharing and collaboration. Based on these findings, we derive stakeholder-specific recommendations for academia, industry, and government to transition HRE from isolated research silos toward a collaborative discipline capable of assuring increasingly complex, global hardware supply chains.

cs.CR

JustSTART: How to Find an RSA Authentication Bypass on Xilinx UltraScale(+) with Fuzzing

Fuzzing is a well-established technique in the software domain to uncover bugs and vulnerabilities. Yet, applications of fuzzing for security vulnerabilities in hardware systems are scarce, as principal reasons are requirements for design information access (HDL source code). Moreover, observation of internal hardware state during runtime is typically an ineffective information source, as its documentation is often not publicly available. In addition, such observation during runtime is also inefficient due to bandwidth-limited analysis interfaces (JTAG, and minimal introspection of internal modules). In this work, we investigate fuzzing for 7-Series and UltraScale(+) FPGA configuration engines, the control plane governing the (secure) bitstream configuration within the FPGA. Our goal is to examine the effectiveness of fuzzing to analyze and document the opaque inner workings of FPGA configuration engines, with a primary emphasis on identifying security vulnerabilities. Using only the publicly available chip and dispersed documentation, we first design and implement ConFuzz, an advanced FPGA configuration engine fuzzing and rapid prototyping framework. Based on our detailed understanding of the bitstream file format, we then systematically define 3 novel key fuzzing strategies for Xilinx configuration engines. Moreover, our strategies are executed through mutational structure-aware fuzzers and incorporate various novel custom-tailored, FPGA-specific optimizations. Our evaluation reveals previously undocumented behavior within the configuration engine, including critical findings such as system crashes leading to unresponsive states of the FPGA. In addition, our investigations not only lead to the rediscovery of the starbleed attack but also uncover JustSTART (CVE-2023-20570), capable of circumventing RSA authentication for Xilinx UltraScale(+). Note that we also discuss countermeasures.

cs.CR