arXiv subjects

Fernando García-Redondo

Publications and source records attributed to Fernando García-Redondo.

5 recordsLinked to original sources

arXiv2026

DTCO of NOR-Type IGZO FeFETs for 3D Heterogeneous AI Memories: A Read-Centric Perspective

InGaZnO (IGZO)-channel FeFETs have attracted notable interest thanks to recent advances in endurance, opening up their application space for read-dominated AI memory tiers. This work evaluates the viability of NOR-type IGZO FeFETs for 3D heterogeneous AI memories from a read-centric design-technology co-optimization (DTCO) perspective, spanning on-chip back-end-of-line (BEOL) RAMs and hybrid-bonded memory chiplets, and off-chip, monolithically integrated 3D FeNOR storage-class memories (SCMs). For on-chip BEOL RAMs and memory chiplets, we demonstrate the cross-node bitcell footprint scalability of IGZO FeFETs capable of delivering down to 10-A SRAM-equivalent bitcell area ($\sim$0.016 $μ$m$^2$) with 7-nm ground rules while maintaining a sub-5 ns random access latency -- despite their writability challenges. We further identify the sensing margin penalty in NOR FeFET arrays arising from sneak current associated with the negative program-state $V_t$, which requires positive-$V_t$ engineering in order to eliminate the unwanted negative voltage read inhibition -- for example, by ferroelectric layer thinning. Last but not least, we elucidate the read margin implications on 3D FeNOR for SCMs, with the 3D stacking density limited by additional sneak current from neighbor channel shunting.

cs.ET↗

arXiv2025

SOT-MRAM Bitcell Scaling with BEOL Read Selectors: A DTCO Study

This work explores the cross-node scaling potential of SOT-MRAM for last-level caches (LLCs) under heterogeneous system scaling paradigm. We perform extensive Design-Technology Co-Optimization (DTCO) exercises to evaluate the bitcell footprint for different cell configurations at a representative 7 nm technology and to assess their implications on read and write power-performance. We crucially identify the MTJ routing struggle in conventional two-transistor one-resistor (2T1R) SOT-MRAMs as the primary bitcell area scaling challenge and propose to use BEOL read selectors (BEOL RSs) that enable (10 -- 40) % bitcell area reduction and eventually match sub-N3 SRAM. On writability, we affirm that BEOL RS-based bitcells could meet the required SOT switching current, provided the magnetic free layer properties be engineered in line with LLC-specific, (0.1 -- 100) s retention targets. This is particularly to attribute to their (i) more available Si fins for write transistor and (ii) lower bitline resistance at reduced cell width. We nevertheless underscore the read tradeoff associated with BEOL RSs, with the low-drive IGZO-FET selector sacrificing the latency up to (3 -- 5) ns and the imperfectly rectifying diode selectors suffering (2.5 -- 5)$\times$ energy cost relative to 2T1R. This article thus highlights the realistic prospects and hurdles of BEOL RSs towards holistic power-performance-area scaling of SOT-MRAM.

cs.ET↗

arXiv2021

A Fokker-Planck Solver to Model MTJ Stochasticity

Magnetic Tunnel Junctions (MTJs) constitute the novel memory element in STT-MRAM, which is ramping to production at major foundries as an eFlash replacement. MTJ switching exhibits a stochastic behavior due to thermal fluctuations, which is modeled by s-LLGS and Fokker-Planck (FP) equations. This work implements and benchmarks Finite Volume Method (FVM) and analytical solvers for the FP equation. To deploy an MTJ model for circuit design, it must be calibrated against silicon data. To address this challenge, this work presents a regression scheme to fit MTJ parameters to a given set of measured current, switching time and error rate data points, yielding a silicon-calibrated model suitable for MRAM macro transient simulation.

cs.ET↗

arXiv2021

A Compact Model for Scalable MTJ Simulation

This paper presents a physics-based modeling framework for the analysis and transient simulation of circuits containing Spin-Transfer Torque (STT) Magnetic Tunnel Junction (MTJ) devices. The framework provides the tools to analyze the stochastic behavior of MTJs and to generate Verilog-A compact models for their simulation in large VLSI designs, addressing the need for an industry-ready model accounting for real-world reliability and scalability requirements. Device dynamics are described by the Landau-Lifshitz-Gilbert-Slonczewsky (s-LLGS ) stochastic magnetization considering Voltage-Controlled Magnetic Anisotropy (VCMA) and the non-negligible statistical effects caused by thermal noise. Model behavior is validated against the OOMMF magnetic simulator and its performance is characterized on a 1-Mb 28 nm Magnetoresistive-RAM (MRAM) memory product.

cs.ET↗

arXiv2020

Training DNN IoT Applications for Deployment On Analog NVM Crossbars

A trend towards energy-efficiency, security and privacy has led to a recent focus on deploying DNNs on microcontrollers. However, limits on compute and memory resources restrict the size and the complexity of the ML models deployable in these systems. Computation-In-Memory architectures based on resistive nonvolatile memory (NVM) technologies hold great promise of satisfying the compute and memory demands of high-performance and low-power, inherent in modern DNNs. Nevertheless, these technologies are still immature and suffer from both the intrinsic analog-domain noise problems and the inability of representing negative weights in the NVM structures, incurring in larger crossbar sizes with concomitant impact on ADCs and DACs. In this paper, we provide a training framework for addressing these challenges and quantitatively evaluate the circuit-level efficiency gains thus accrued. We make two contributions: Firstly, we propose a training algorithm that eliminates the need for tuning individual layers of a DNN ensuring uniformity across layer weights and activations. This ensures analog-blocks that can be reused and peripheral hardware substantially reduced. Secondly, using NAS methods, we propose the use of unipolar-weighted (either all-positive or all-negative weights) matrices/sub-matrices. Weight unipolarity obviates the need for doubling crossbar area leading to simplified analog periphery. We validate our methodology with CIFAR10 and HAR applications by mapping to crossbars using 4-bit and 2-bit devices. We achieve up to 92:91% accuracy (95% floating-point) using 2-bit only-positive weights for HAR. A combination of the proposed techniques leads to 80% area improvement and up to 45% energy reduction.

cs.LG↗