arXiv subjects

Fernando Garcia Redondo

Publications and source records attributed to Fernando Garcia Redondo.

3 recordsLinked to original sources

arXiv2026

From sLLG to Fokker-Planck: Accurate WER Modeling for Non-Axisymmetric MRAM Devices

The Fokker--Planck (FP) equation is essential for predicting write error rates (WER) in STT and SOT-MRAM devices, but traditional 1D projections fail when symmetry is broken by in-plane fields, field-like torques, or anisotropic barriers. We develop a 2D finite-volume (FVM) solver on the unit sphere and validate it against $10^6$-trajectory stochastic Landau--Lifshitz--Gilbert (sLLG) simulations. The solver supports four discretization schemes---central, Scharfetter--Gummel (SG), upwind, and hybrid adaptive blending---each with different Péclet-dependent accuracy and monotonicity properties. We demonstrate that central differencing recovers ground-truth WER for STT and SOT geometries where 2D effects dominate, and show that the choice of discretization scheme directly affects predicted WER. For magnetic simulations, we recommend hybrid adaptive blending as the optimal balance of accuracy and stability across variable Péclet regimes. These results establish that customizable discretization is critical for accurate, unbiased predictions of switching dynamics in next-generation magnetic memory.

cs.ET↗

arXiv2025

AbbIE: Autoregressive Block-Based Iterative Encoder for Efficient Sequence Modeling

We introduce the Autoregressive Block-Based Iterative Encoder (AbbIE), a novel recursive generalization of the encoder-only Transformer architecture, which achieves better perplexity than a standard Transformer and allows for the dynamic scaling of compute resources at test time. This simple, recursive approach is a complement to scaling large language model (LLM) performance through parameter and token counts. AbbIE performs its iterations in latent space, but unlike latent reasoning models, does not require a specialized dataset or training protocol. We show that AbbIE upward generalizes (ability to generalize to arbitrary iteration lengths) at test time by only using 2 iterations during train time, far outperforming alternative iterative methods. AbbIE's ability to scale its computational expenditure based on the complexity of the task gives it an up to \textbf{12\%} improvement in zero-shot in-context learning tasks versus other iterative and standard methods and up to 5\% improvement in language perplexity. The results from this study open a new avenue to Transformer performance scaling. We perform all of our evaluations on model sizes up to 350M parameters.

cs.LG↗

arXiv2021

AnalogNets: ML-HW Co-Design of Noise-robust TinyML Models and Always-On Analog Compute-in-Memory Accelerator

Always-on TinyML perception tasks in IoT applications require very high energy efficiency. Analog compute-in-memory (CiM) using non-volatile memory (NVM) promises high efficiency and also provides self-contained on-chip model storage. However, analog CiM introduces new practical considerations, including conductance drift, read/write noise, fixed analog-to-digital (ADC) converter gain, etc. These additional constraints must be addressed to achieve models that can be deployed on analog CiM with acceptable accuracy loss. This work describes $\textit{AnalogNets}$: TinyML models for the popular always-on applications of keyword spotting (KWS) and visual wake words (VWW). The model architectures are specifically designed for analog CiM, and we detail a comprehensive training methodology, to retain accuracy in the face of analog non-idealities, and low-precision data converters at inference time. We also describe AON-CiM, a programmable, minimal-area phase-change memory (PCM) analog CiM accelerator, with a novel layer-serial approach to remove the cost of complex interconnects associated with a fully-pipelined design. We evaluate the AnalogNets on a calibrated simulator, as well as real hardware, and find that accuracy degradation is limited to 0.8$\%$/1.2$\%$ after 24 hours of PCM drift (8-bit) for KWS/VWW. AnalogNets running on the 14nm AON-CiM accelerator demonstrate 8.58/4.37 TOPS/W for KWS/VWW workloads using 8-bit activations, respectively, and increasing to 57.39/25.69 TOPS/W with $4$-bit activations.

cs.AR↗