arXiv subjects

Florian K. Unseld

Publications and source records attributed to Florian K. Unseld.

6 recordsLinked to original sources

arXiv2026

Dispersive Readout of a SiMOS Quantum Dot Using a Flip-Chip Integrated Microwave Resonator

Heterogeneous integration provides a promising route to combine semiconductor quantum dot devices and superconducting microwave circuits, while allowing each component to be fabricated using an optimized process flow. Here, we demonstrate a flip-chip integrated platform for dispersive readout of silicon metal-oxide semiconductor (SiMOS) quantum dot devices. A SiMOS double quantum dot chip is bonded to a superconducting aluminum resonator chip using indium bump interconnects to enable microwave coupling to the quantum dot gate. We show that the developed flip-chip process is compatible with cryogenic operation of both the SiMOS device and the superconducting resonator, and demonstrate resonator-based detection of charge transitions in the quantum dot system. The readout signal-to-noise ratio follows a dependence of $\sqrt{t}$ with the integration time, reaching SNR = 1 at an integration time of approximately 0.3 ms. These results establish flip-chip bonding as a viable integration approach for SiMOS quantum dot devices operating at both dc and microwave frequencies, with potential applications for resonator-based techniques such as spin-photon coupling.

cond-mat.mes-hall↗

arXiv2026

SiMOS quantum-dot spin qubits enabled by extreme-ultraviolet lithography

The realization of large-scale silicon quantum processors requires spin qubits compatible with advanced semiconductor manufacturing technologies, demanding lithographic processes that combine nanometer-scale precision with exceptional uniformity. Although the highest-performing silicon spin qubits demonstrated to date have relied on electron-beam (e-beam) lithography, its serial exposure process limits reproducibility studies and wafer-scale fabrication. Here, we demonstrate high-performance silicon metal-oxide-semiconductor (SiMOS) spin qubits fabricated using extreme-ultraviolet (EUV) lithography in a 300 mm semiconductor pilot line. We report wafer-scale quantum-dot uniformity metrics, including 100 % room-temperature gate-to-gate leakage yield and sub-nanometer control of critical gate dimensions. We characterize four double-dot systems realized in two triple-quantum-dot devices. Gate set tomography (GST) reveals consistently high fidelities across all four systems, with values up to 99.8 % for SPAM, 99.9 % for single-qubit gates, and 99.1 % for two-qubit gates. The devices exhibit highly reproducible exchange turn-on characteristics of 10-13 dec/V, indicating high fabrication uniformity enabled by EUV patterning. These results establish EUV lithography as a viable manufacturing technology for quantum processors based on high-fidelity SiMOS spin qubits.

cond-mat.mes-hall↗

arXiv2025

Tracking spin qubit frequency variations over 912 days

Solid-state qubits are sensitive to their microscopic environment, causing the qubit properties to fluctuate on a wide range of timescales. The sub-Hz end of the spectrum is usually dealt with by repeated background calibrations, which bring considerable overhead. It is thus important to characterize and understand the low-frequency variations of the relevant qubit characteristics. In this study, we investigate the stability of spin qubit frequencies in the Si/SiGe quantum dot platform. We find that the calibrated qubit frequencies of a six-qubit device vary by up to $\pm 100$ MHz while performing a variety of experiments over a span of 912 days. These variations are sensitive to the precise voltage settings of the gate electrodes, however when these are kept constant to within 15 $\mathrmμ$V, the qubit frequencies vary by less than $\pm 7$ MHz over periods up to 36 days. During overnight scans, the qubit frequencies of ten qubits across two different devices show a standard deviation below 200 kHz within a 1-hour time window. The qubit frequency noise spectral density shows roughly a $1/f$ trend above $10^{-4}$ Hz and, strikingly, a steeper trend at even lower frequencies.

cond-mat.mes-hall↗

arXiv2024

Baseband control of single-electron silicon spin qubits in two dimensions

Micromagnet-enabled electric-dipole spin resonance (EDSR) is an established method of high-fidelity single-spin control in silicon. However, the resulting architectural limitations have restrained silicon quantum processors to one-dimensional arrays, and heating effects from the associated microwave dissipation exacerbates crosstalk during multi-qubit operations. In contrast, qubit control based on hopping spins has recently emerged as a compelling primitive for high-fidelity baseband control in sparse two-dimensional hole arrays in germanium. In this work, we commission a $^{28}$Si/SiGe 2x2 quantum dot array both as a four-qubit device with pairwise exchange interactions using established EDSR techniques and as a two-qubit device using baseband hopping control. In this manner, we can evaluate the two modes of operation in terms of fidelity, coherence, and crosstalk. We establish a lower bound on the fidelity of the hopping gate of 99.50(6)%, which is similar to the average fidelity of the resonant gate of 99.54(4)%. Lowering the external field to reach the hopping regime nearly doubles the measured $T_2^{\mathrm{H}}$, suggesting a reduced coupling to charge noise. Finally, the hopping gate circumvents the transient pulse-induced resonance shift. To further motivate the hopping gate approach as an attractive means of scaling silicon spin-qubit arrays, we propose an extensible nanomagnet design that enables engineered baseband control of large spin arrays.

cond-mat.mes-hall↗

arXiv2023

Single-electron occupation in quantum dot arrays at selectable plunger gate voltage

The small footprint of semiconductor qubits is favourable for scalable quantum computing. However, their size also makes them sensitive to their local environment and variations in gate structure. Currently, each device requires tailored gate voltages to confine a single charge per quantum dot, clearly challenging scalability. Here, we tune these gate voltages and equalize them solely through the temporary application of stress voltages. In a double quantum dot, we reach a stable (1,1) charge state at identical and predetermined plunger gate voltage and for various interdot couplings. Applying our findings, we tune a 2$\times$2 quadruple quantum dot such that the (1,1,1,1) charge state is reached when all plunger gates are set to 1 V. The ability to define required gate voltages may relax requirements on control electronics and operations for spin qubit devices, providing means to advance quantum hardware.

cond-mat.mes-hall↗

arXiv2023

A 2D quantum dot array in planar $^{28}$Si/SiGe

Semiconductor spin qubits have gained increasing attention as a possible platform to host a fault-tolerant quantum computer. First demonstrations of spin qubit arrays have been shown in a wide variety of semiconductor materials. The highest performance for spin qubit logic has been realized in silicon, but scaling silicon quantum dot arrays in two dimensions has proven to be challenging. By taking advantage of high-quality heterostructures and carefully designed gate patterns, we are able to form a tunnel coupled 2 $\times$ 2 quantum dot array in a $^{28}$Si/SiGe heterostructure. We are able to load a single electron in all four quantum dots, thus reaching the (1,1,1,1) charge state. Furthermore we characterise and control the tunnel coupling between all pairs of dots by measuring polarisation lines over a wide range of barrier gate voltages. Tunnel couplings can be tuned from about $30~\rm μeV$ up to approximately $400~\rm μeV$. These experiments provide a first step toward the operation of spin qubits in $^{28}$Si/SiGe quantum dots in two dimensions.

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