arXiv subjects

Fumihiko Ino

Publications and source records attributed to Fumihiko Ino.

9 recordsLinked to original sources

arXiv2026

Square-root Time Atom Reconfiguration Plan for Lattice-shaped Mobile Tweezers

This paper proposes a scalable planning algorithm for creating defect-free atom arrays in neutral-atom systems. The algorithm generates a $\mathcal{O}(\sqrt N)$ time plan for $N$ atoms by parallelizing atom transport using a two-dimensional lattice pattern generated by acousto-optic deflectors. Our approach is based on a divide-and-conquer strategy that decomposes an arbitrary reconfiguration problem into at most three one-dimensional shuttling tasks, enabling each atom to be transported with a total transportation cost of $\mathcal{O}(\sqrt N)$. Using the Gale--Ryser theorem, the proposed algorithm provides a highly reliable solution for arbitrary target geometries. We further introduce a peephole optimization technique that improves reconfiguration efficiency for grid target geometries. Numerical simulations on a 632$\times$632 atom array demonstrate that the proposed algorithm achieves a grid configuration plan that reduces the total transportation cost to 1/7 of state-of-the-art algorithms, while resulting in 32%--35% more atom captures. We believe that our scalability improvement contributes to realizing large-scale quantum computers based on neutral atoms. Our experimental code is available from https://github.com/kotamanegi/sqrt-time-atom-reconfigure.

quant-ph↗

arXiv2024

Lazy Qubit Reordering for Accelerating Parallel State-Vector-based Quantum Circuit Simulation

This paper proposes two quantum operation scheduling methods for accelerating parallel state-vector-based quantum circuit simulation using multiple graphics processing units (GPUs). The proposed methods reduce all-to-all communication caused by qubit reordering (QR), which can dominate the overhead of parallel simulation. Our approach eliminates redundant QRs by introducing intentional delays in QR communications such that multiple QRs can be aggregated into a single QR. The delays are carefully introduced based on the principles of time-space tiling, or a cache optimization technique for classical computers, which we use to arrange the execution order of quantum operations. Moreover, we present an extended scheduling method for the hierarchical interconnection of GPU cluster systems to avoid slow inter-node communication. We develop these methods tailored for two primary procedures in variational quantum eigensolver (VQE) simulation: quantum state update (QSU) and expectation value computation (EVC). Experimental validation on 32-GPU executions demonstrates acceleration in QSU and EVC -- up to 54$\times$ and 606$\times$, respectively -- compared to existing methods. Moreover, our extended scheduling method further reduced communication time by up to 15\% in a two-layered interconnected cluster system. Our approach is useful for any quantum circuit simulations, including QSU and/or EVC.

quant-ph↗

arXiv2023

A Synergy between On- and Off-Chip Data Reuse for GPU-based Out-of-Core Stencil Computation

Stencil computation is an extensively-utilized class of scientific-computing applications that can be efficiently accelerated by graphics processing units (GPUs). Out-of-core approaches enable a GPU to handle large stencil codes whose data size is beyond the memory capacity of the GPU. However, current research on out-of-core stencil computation primarily focus on minimizing the amount of data transferred between the CPU and GPU. Few studies consider simultaneously optimizing data transfer and kernel execution. To fill the research gap, this work presents a synergy between on- and off-chip data reuse for out-of-core stencil codes, termed SO2DR. First, overlapping regions between data chunks are shared in the off-chip memory to eliminate redundant CPU-GPU data transfer. Secondly, redundant computation at the off-chip memory level is intentionally introduced to decouple kernel execution from region sharing, hence enabling data reuse in the on-chip memory. Experimental results demonstrate that SO2DR significantly enhances the kernel-execution performance while reducing the CPU-GPU data-transfer time. Specifically, SO2DR achieves average speedups of 2.78x and 1.14x for five stencil benchmarks, compared to an out-of-core stencil code which is free of redundant transfer and computation, and an in-core stencil code which is free of data transfer, respectively.

cs.DC↗

arXiv2022

A Reorder Trick for Decision Diagram Based Quantum Circuit Simulation

Quantum computing is a hotspot technology for its potential to accelerate specific applications by exploiting quantum parallelism. However, current physical quantum computers are limited to a relatively small scale, simulators based on conventional machines are significantly relied on to perform quantum computing research. The straightforward array-based simulators require a tremendous amount of memory that increases exponentially with respect to the number of qubits. To mitigate such computing resource concerns, decision diagram based simulators were proposed that can efficiently exploit data redundancies in quantum states and operations. In this paper, we study two classes of quantum circuits on which the state-of-the-art decision diagram based simulators failed to perform well in terms of simulation time. We also propose a simple and powerful reorder trick to boost the simulation of such quantum circuits. Preliminary evaluation results demonstrate the usefulness of the proposed trick. Especially, for the Quantum Phase Estimation circuits, the proposed trick achieved speedups up to 313.6x compared to a state-of-the-art approach that relies on an auxiliary tool to optimize simulation order.

quant-ph↗

arXiv2022

A One-Shot Reparameterization Method for Reducing the Loss of Tile Pruning on DNNs

Recently, tile pruning has been widely studied to accelerate the inference of deep neural networks (DNNs). However, we found that the loss due to tile pruning, which can eliminate important elements together with unimportant elements, is large on trained DNNs. In this study, we propose a one-shot reparameterization method, called TileTrans, to reduce the loss of tile pruning. Specifically, we repermute the rows or columns of the weight matrix such that the model architecture can be kept unchanged after reparameterization. This repermutation realizes the reparameterization of the DNN model without any retraining. The proposed reparameterization method combines important elements into the same tile; thus, preserving the important elements after the tile pruning. Furthermore, TileTrans can be seamlessly integrated into existing tile pruning methods because it is a pre-processing method executed before pruning, which is orthogonal to most existing methods. The experimental results demonstrate that our method is essential in reducing the loss of tile pruning on DNNs. Specifically, the accuracy is improved by up to 17% for AlexNet while 5% for ResNet-34, where both models are pre-trained on ImageNet.

cs.CV↗

arXiv2022

Compression-Based Optimizations for Out-of-Core GPU Stencil Computation

An out-of-core stencil computation code handles large data whose size is beyond the capacity of GPU memory. Whereas, such an code requires streaming data to and from the GPU frequently. As a result, data movement between the CPU and GPU usually limits the performance. In this work, compression-based optimizations are proposed. First, an on-the-fly compression technique is applied to an out-of-core stencil code, reducing the CPU-GPU memory copy. Secondly, a single working buffer technique is used to reduce GPU memory consumption. Experimental results show that the stencil code using the proposed techniques achieved 1.1x speed and reduced GPU memory consumption by 33.0\% on an NVIDIA Tesla V100 GPU.

cs.DC↗

arXiv2021

Accelerating GPU-Based Out-of-Core Stencil Computation with On-the-Fly Compression

Stencil computation is an important class of scientific applications that can be efficiently executed by graphics processing units (GPUs). Out-of-core approach helps run large scale stencil codes that process data with sizes larger than the limited capacity of GPU memory. However, the performance of the GPU-based out-of-core stencil computation is always limited by the data transfer between the CPU and GPU. Many optimizations have been explored to reduce such data transfer, but the study on the use of on-the-fly compression techniques is far from sufficient. In this study, we propose a method that accelerates the GPU-based out-of-core stencil computation with on-the-fly compression. We introduce a novel data compression approach that solves the data dependency between two contiguous decomposed data blocks. We also modify a widely used GPU-based compression library to support pipelining that overlaps CPU/GPU data transfer with GPU computation. Experimental results show that the proposed method achieved a speedup of 1.2x compared the method without compression. Moreover, although the precision loss involved by compression increased with the number of time steps, the precision loss was trivial up to 4,320 time steps, demonstrating the usefulness of the proposed method.

cs.DC↗

arXiv2017

High-Performance Out-of-core Block Randomized Singular Value Decomposition on GPU

Fast computation of singular value decomposition (SVD) is of great interest in various machine learning tasks. Recently, SVD methods based on randomized linear algebra have shown significant speedup in this regime. This paper attempts to further accelerate the computation by harnessing a modern computing architecture, namely graphics processing unit (GPU), with the goal of processing large-scale data that may not fit in the GPU memory. It leads to a new block randomized algorithm that fully utilizes the power of GPUs and efficiently processes large-scale data in an out-of- core fashion. Our experiment shows that the proposed block randomized SVD (BRSVD) method outperforms existing randomized SVD methods in terms of speed with retaining the same accuracy. We also show its application to convex robust principal component analysis, which shows significant speedup in computer vision applications.

cs.DC↗

arXiv2003

Debugging Tool for Localizing Faulty Processes in Message Passing Programs

In message passing programs, once a process terminates with an unexpected error, the terminated process can propagate the error to the rest of processes through communication dependencies, resulting in a program failure. Therefore, to locate faults, developers must identify the group of processes involved in the original error and faulty processes that activate faults. This paper presents a novel debugging tool, named MPI-PreDebugger (MPI-PD), for localizing faulty processes in message passing programs. MPI-PD automatically distinguishes the original and the propagated errors by checking communication errors during program execution. If MPI-PD observes any communication errors, it backtraces communication dependencies and points out potential faulty processes in a timeline view. We also introduce three case studies, in which MPI-PD has been shown to play the key role in their debugging. From these studies, we believe that MPI-PD helps developers to locate faults and allows them to concentrate in correcting their programs.

cs.SE↗