arXiv subjects

G. Huang

Publications and source records attributed to G. Huang.

At least 19 recordsLinked to original sources

arXiv2025

Development of non amplified Depleted MAPS sensors towards 50 ps timing resolution on charged particles

The MiniCactus sensors are demonstrator sensors designed in LFoundry LF15A 150 nm technology, intended to study the performance of non amplified High Voltage High Resistivity CMOS sensors for measurement of time of arrival of charged particles. This paper presents the context, design features and some of the first test-beam results obtained with the latest MiniCactus sensor version, MiniCactus V2. With a 175 micron thick sensor biased at -350 V, we have obtained a 60 ps time resolution on Minimum Ionizing Particles detected with a 500 micron by 500 micron pixel.

physics.ins-det↗

arXiv2024

Long time regularity of the $p$-Gauss curvature flow with flat side

In this paper, we prove the long time regularity of the interface in the $p$-Gauss curvature flow with flat side in all dimensions for $p>\frac1n$. Here the interface is the boundary of the flat part in the flow. In dimension $2$, this problem was solved in \cite{DL2004} for $p=1$ and in \cite{KimLeeRhee2013} for $p\in(1/2,1)$. We utilize the duality method to transform the Gauss curvature flow to a singular parabolic Monge-Amp\`ere equation, and prove the regularity of the interface by studying the asymptotic cone of the parabolic Monge-Amp\`ere equation in the polar coordinates.

math.AP↗

arXiv2023

GBT20, a 20.48 Gbps PAM4 Optical Transmitter Module for Particle Physics Experiments

We present a pluggable radiation-tolerant 4-level Pulse-Amplitude-Modulation (PAM4) optical transmitter module called GBT20 (Giga-Bit Transmitter at 20 Gbps) for particle-physics experiments. GBT20 has an OSFP or firefly connector to input 16-bit data each at 1.28 Gbps. The GBT20 drives a VCSEL die with an LC lens or a VCSEL TOSA and interfaces an optical fiber with a standard LC connector. The minimum module, including the host connector, occupies 41 mm x 13 mm x 6 mm. At 20.48 Gbps, the minimum Transmitter Dispersion Eye Closure Quaternary (TDECQ) is around 0.7 dB. The power consumption is around 164 mW in the low-power mode. The SEE cross-section is below 7.5x10^(-14) cm^2. No significant performance degrades after a TID of 5.4 kGy.

physics.ins-det↗

arXiv2023

The design and test results of A Giga-Bit Cable Receiver (GBCR) for the ATLAS Inner Tracker Pixel Detector

This paper presents the design and test results of a Gigabit Cable Receiver ASIC called GBCR for the HL-LHC upgrade of the ATLAS Inner Tracker (ITk) pixel detector. Three prototypes (GBCR1, GBCR2, and GBCR3) have been designed in the CERN-identified 65 nm CMOS technology. GBCR receives seven (GBCR2) or six (GBCR3) channels (RX) each at 1.28 Gbps from the front-end readout chip RD53B via flex cables up to 1 meter and Twinax cables up to 5 meters and sends the equalized and retimed signals to lpGBT. Both GBCR2 and GBCR3 ASICs have two transmitting channels (TX) that pre-emphasize the signals from lpGBT before sending them to RD53B through the same cables. No Single-Event Upset (SEU) is observed in any tested channels of GBCR2 in a 400 MeV proton beam. The extrapolated bit error rate for the future HL-LHC application is below 8*10^(-16), significantly below the specified BER criterion. GBCR3 is designed to improve the immunity to single-event-upset by applying the Triple Modular Redundancy (TMR) technology to all RX channels. The retimed signals from GBCR3 have less total jitter than those from GBCR2 (35 ps versus 79 ps). Each receiver channel of GBCR3 consumes 75% more power than that of GBCR2.

physics.ins-det↗

arXiv2022

Interactivism in Spoken Dialogue Systems

The interactivism model introduces a dynamic approach to language, communication and cognition. In this work, we explore this fundamental theory in the context of dialogue modelling for spoken dialogue systems (SDS). To extend such a theoretical framework, we present a set of design principles which adhere to central psycholinguistic and communication theories to achieve interactivism in SDS. From these, key ideas are linked to constitute the basis of our proposed design principles.

cs.CL↗

arXiv2022

A 40 Gbps Optical Transceiver for Particle Physics Experiments

We present the design and the test results of a quad-channel optical transceiver module (QTRx) possibly for future particle physics experiments. The transmitters of QTRx, each at 10 Gbps, are based on a Quad-channel VCSEL Diode array Driver (QLDD) and 1 x 4 VCSEL array. The receivers of QTRx, with data rates of 2.56 Gbps or 10 Gbps per channel, are based on a Quad-channel Trans-Impedance and limiting Amplifier (QTIA) and 1 x 4 photodiode array of GaAs or InGaAs. QTRx is 20 mm x 10 mm x 5 mm and couples to an MT fiber connector. Test results indicate that QTRx achieves the design goals with a power consumption of 124 mW per transmitter channel at 10 Gbps and 120 mW at 2.56 Gbps for the receiver channel with an on-chip charge pump. The sensitivities of QTIA are -17 dBm at 2.56 Gbps and -8 dBm at 10 Gbps, respectively. Further improvements with a gold-finger interface and a more compact optical lens are being designed.

physics.ins-det↗

arXiv2022

Cavity-mediated electron-photon pairs

Advancing quantum information, communication and sensing relies on the generation and control of quantum correlations in complementary degrees of freedom. Here, we demonstrate the preparation of electron-photon pair states using the phase-matched interaction of free electrons with the evanescent vacuum field of a photonic-chip-based optical microresonator. Spontaneous inelastic scattering produces intracavity photons coincident with energy-shifted electrons. Harnessing these pairs for correlation-enhanced imaging, we achieve a two-orders of magnitude contrast improvement in cavity-mode mapping by coincidence-gated electron spectroscopy. This parametric pair-state preparation will underpin the future development of free-electron quantum optics, providing a pathway to quantum-enhanced imaging, electron-photon entanglement, and heralded single-electron and Fock-state photon sources.

quant-ph↗

arXiv2022

A radiation tolerant clock generator for the CMS Endcap Timing Layer readout chip

We present the test results of a low jitter Phase Locked Loop (PLL) prototype chip for the CMS Endcap Timing Layer readout chip (ETROC). This chip is based on the improved version of a clock synthesis circuit named ljCDR from the Low-Power Gigabit Transceiver (lpGBT) project. The ljCDR is tested in its PLL mode. An automatic frequency calibration (AFC) block with the Triple Modular Redundancy (TMR) register is developed for the LC-oscillator calibration. The chip was manufactured in a 65 nm CMOS process with 10 metal layers. The chip has been extensively tested, including Total Ionizing Dose (TID) testing up to 300 Mrad and Single Event Upset (SEU) testing with heavy ions possessing a Linear energy transfer (LET) from 1.3 to 62.5 MeV*cm^2/mg.

physics.ins-det↗

arXiv2022

QTIA, a 2.5 or 10 Gbps 4-Channel Array Optical Receiver ASIC in a 65 nm CMOS Technology

The Quad transimpedance and limiting amplifier (QTIA) is a 4-channel array optical receiver ASIC, developed using a 65 nm CMOS process. It is configurable between the bit rate of 2.56 Gbps and 10 Gbps per channel. QTIA offers careful matching to both GaAs and InGaAs photodiodes. At this R&D stage, each channel has a different biasing scheme to the photodiode for optimal coupling. A charge pump is implemented in one channel to provide a higher reverse bias voltage, which is especially important to mitigate radiation effects on the photodiodes. The circuit functions of QTIA successfully passed the lab tests with GaAs photodiodes.

physics.ins-det↗

arXiv2022

A 20 Gbps PAM4 Data Transmitter ASIC for Particle Physics Experiments

We present the design and test results of a novel data transmitter ASIC operating up to 20.48 Gbps with 4-level Pulse-Amplitude-Modulation (PAM4) for particle physics experiments. This ASIC, named GBS20, is fabricated in a 65 nm CMOS technology. Two serializers share a 5.12 GHz Phase Locked Loop (PLL) clock. The outputs from the serializers are combined into a PAM4 signal that directly drives a Vertical-Cavity-Surface-Emitting-Laser (VCSEL). The input data channels, each at 1.28 Gbps, are scrambled with an internal 27-1 Pseudo-Random Binary Sequence (PRBS), which also serves as a frame aligner. GBS20 is tested to work at 10.24 and 20.48 Gbps with a VCSEL-based Transmitter-Optical-Subassembly (TOSA). The power consumption of GBS20 is below 238 mW and reduced to 164 mW in the low-power mode.

physics.ins-det↗

arXiv2021

The TaichuPix1: A Monolithic Active Pixel Sensor with fast in-pixel readout electronics for the CEPC vertex detector

The proposed Circular Electron Positron Collider (CEPC) imposes new challenges for the vertex detector in terms of high resolution, low material, fast readout and low power. The Monolithic Active Pixel Sensor (MAPS) technology has been chosen as one of the most promising candidates to satisfy these requirements. A MAPS prototype, called TaichuPix1, based on a data-driven structure, together with a column drain readout architecture, benefiting from the ALPIDE and FE-I3 approaches, has been implemented to achieve fast readout. This paper presents the overall architecture of TaichuPix1, the experimental characterization of the FE-I3-like matrix, the threshold dispersion, the noise distribution of the pixels and verifies the charge collection using a radioactive source. These results prove the functionality of the digital periphery and serializer are able to transmit the collected charge to the data interface correctly. Moreover, the individual self-tests of the serializer verify it can work up to about 3 Gbps. And it also indicates that the analog front-end features a fast-rising signal with a short time walk and that the FE-I3-like in-pixel digital logic is properly operating at the 40 MHz system clock.

physics.ins-det↗

arXiv2021

In-pixel automatic threshold calibration for the CMS Endcap Timing Layer readout chip

We present the implementation and verification of an in-pixel automatic threshold calibration circuit for the CMS Endcap Timing Layer (ETL) in the High-Luminosity LHC upgrade. The discriminator threshold of the ETL readout chip (ETROC) needs to be calibrated regularly to mitigate the circuit baseline change. Traditional methods need a lot of communication through a slow control system hence are time-consuming. This paper describes an in-pixel automatic scheme with improvements in operating time and usability. In this scheme, a sample-accumulation circuit is used to measure the average discriminator output. A binary successive approximation and linear combination scan are applied to find the equivalent baseline. The actual calibration procedure has been first implemented in FPGA firmware and tested with the ETROC front-end prototype chip (ETROC0). The calibration circuit has been implemented with Triple Modular Redundancy (TMR) and verified with Single Event Effects (SEEs) simulation. A complete calibration process lasts 35 ms with a 40 MHz clock. In the worst case, the dynamic and static power consumption are estimated to be 300 uW and 10.4 uW, respectively. The circuit design, implemented in a 65 CMOS technology, will be integrated into ETROC2, the next iteration of the ETROC with a 16x16 pixel matrix.

physics.ins-det↗

arXiv2021

First demonstration of in-beam performance of bent Monolithic Active Pixel Sensors

A novel approach for designing the next generation of vertex detectors foresees to employ wafer-scale sensors that can be bent to truly cylindrical geometries after thinning them to thicknesses of 20-40$μ$m. To solidify this concept, the feasibility of operating bent MAPS was demonstrated using 1.5$\times$3cm ALPIDE chips. Already with their thickness of 50$μ$m, they can be successfully bent to radii of about 2cm without any signs of mechanical or electrical damage. During a subsequent characterisation using a 5.4GeV electron beam, it was further confirmed that they preserve their full electrical functionality as well as particle detection performance. In this article, the bending procedure and the setup used for characterisation are detailed. Furthermore, the analysis of the beam test, including the measurement of the detection efficiency as a function of beam position and local inclination angle, is discussed. The results show that the sensors maintain their excellent performance after bending to radii of 2cm, with detection efficiencies above 99.9% at typical operating conditions, paving the way towards a new class of detectors with unprecedented low material budget and ideal geometrical properties.

physics.ins-det↗

arXiv2021

Characterization and quality control test of a gigabit cable receiver ASIC (GBCR2) for the ATLAS Inner Tracker Detector upgrade

We present the characterization and quality control test of a gigabit cable receiver ASIC prototype, GBCR2, for the ATLAS Inner Tracker pixel detector upgrade. GBCR2 equalizes and retimes the uplink electrical signals from RD53B through a 6 m Twinax AWG34 cable to lpGBT. GBCR2 also pre-emphasizes downlink command signals through the same electrical connection from lpGBT to RD53B. GBCR2 has seven uplink channels each at 1.28 Gbps and two downlink channels each at 160 Mbps. The prototype is fabricated in a 65 nm CMOS process. The characterization of GBCR2 has been demonstrated that the total jitter of the output signal is 129.1 ps (peak-peak) in the non-retiming mode or 79.3 ps (peak-peak) in the retiming mode for the uplink channel and meets the requirements of lpGBT. The total power consumption of all uplink channels is 87.0 mW in the non-retiming mode and 101.4 mW in the retiming mode, below the specification of 174 mW. The two downlink channels consume less than 53 mW. A quality control test procedure is proposed and 169 prototype chips are tested. The yield is about 97.0%.

physics.ins-det↗

arXiv2021

Integrated photonics enables continuous-beam electron phase modulation

The ability to tailor laser light on a chip using integrated photonics has allowed for extensive control over fundamental light-matter interactions in manifold quantum systems including atoms, trapped ions, quantum dots, and defect centers. Free electrons, enabling high-resolution microscopy for decades, are increasingly becoming the subject of laser-based quantum manipulation. Using free-space optical excitation and intense laser pulses, this has led to the observation of free-electron quantum walks, attosecond electron pulses, and imaging of electromagnetic fields. Enhancing the interaction with electron beams through chip-based photonics promises unique applications in nanoscale quantum control and sensing, but has yet to enter electron microscopy. Here, we merge integrated photonics with electron microscopy, demonstrating coherent phase modulation of an electron beam using a silicon nitride microresonator driven by a continuous-wave laser. The high-Q factor (~$10^6$) cavity enhancement and a waveguide designed for phase matching lead to efficient electron-light scattering at unprecedentedly low, few-microwatt optical powers. Specifically, we fully deplete the initial electron state at a cavity-coupled power of 6 $μ$W and create >500 photon sidebands for only 38 mW in the bus waveguide. Moreover, we demonstrate $μ$eV electron energy gain spectroscopy (EEGS). Providing simultaneous optical and electronic spectroscopy of the resonant cavity, the fiber-coupled photonic structures feature single-mode electron-light interaction with full control over the input and output channels. This approach establishes a versatile framework for exploring free-electron quantum optics, with future developments in strong coupling, local quantum probing, and electron-photon entanglement. Our results highlight the potential of integrated photonics to efficiently interface free electrons and light.

physics.optics↗

arXiv2020

A novel quad-channel 10 Gbps CMOS VCSEL array driver with integrated charge pumps

We present a novel design and the test results of a 4-channel driver for an array of Vertical-Cavity Surface-Emitting Lasers (VCSELs). This ASIC, named cpVLAD and fabricated in a 65 nm CMOS technology, has on-chip charge pumps and is for data rates up to 10 Gbps per channel. The charge pumps are implemented to address the issue of voltage margin of the VCSEL driving stage in the applications under low temperature and harsh radiation environment. Test results indicate that cpVLAD is capable of driving VCSELs with forward voltages of up to 2.8 V using 1.2 V and 2.5 V power supplies with a power consumption of 94 mW/channel.

physics.ins-det↗

arXiv2020

Iterative Retina for high track multiplicity in a barrel-shape tracker and high magnetic field

Real-time track tracking in high energy physics experiments at colliders running at high luminosity is very challenging for trigger systems. To perform pattern-recognition and track fitting in online trigger system, the artificial Retina algorithm has been introduced in the field. Retina can be implemented in the state of the art FPGA devices. Our developments use Retina in an iterative way to identify track for barrel-shape tracker embedded in a high magnetic field and with high track multiplicity. As a benchmark we simulate LHC t-tbar events, with a pile-up of 200 and a GEANT-4 based simulation of a 6-layers barrel tracker detector made of silicon modules. With this sample the performance of the hardware design (resource usage, latency) is evaluated. Both efficiency and purity of the Retina fitting are over 90%. Moreover we have also added a Kalman filter after the Retina fit to improve the resolution on the track parameters. Our simulation results show that the Kalman filter can work well together with the Retina algorithm to find track through t-tbar event and provides high resolutions of the reconstructed parameters.

physics.ins-det↗

arXiv2020

A gigabit transceiver for the ATLAS inner tracker pixel detector readout upgrade

This paper presents the design and simulation results of a gigabit transceiver Application Specific Integrated Circuit (ASIC) called GBCR for the ATLAS Inner Tracker (ITk) Pixel detector readout upgrade. GBCR has four upstream receiver channels and a downstream transmitter channel. Each upstream channel operates at 5.12 Gbps, while the downstream channel operates at 2.56 Gbps. In each upstream channel, GBCR equalizes a signal received through a 5-meter 34-American Wire Gauge (AWG) twin-axial cable, retimes the data with a recovered clock, and drives an optical transmitter. In the downstream channel, GBCR receives the data from an optical receiver and drives the same type of cable as the upstream channels. The output jitter of an upstream channel is 26.5 ps and the jitter of the downstream channel after the cable is 33.5 ps. Each upstream channel consumes 78 mW and each downstream channel consumes 27 mW. Simulation results of the upstream test channel suggest that a significant jitter reduction could be achieved with minimally increased power consumption by using a Feed Forward Equalizer (FFE) + Decision Feedback Equalization (DFE) in addition to the linear equalization of the baseline channel. GBCR is designed in a 65-nm CMOS technology.

physics.ins-det↗