Gholamreza Zare Fatin

arXiv2023

Area- Efficient VLSI Implementation of Serial-In Parallel-Out Multiplier Using Polynomial Representation in Finite Field GF(2m)

Finite field multiplier is mainly used in error-correcting codes and signal processing. Finite field multiplier is regarded as the bottleneck arithmetic unit for such applications and it is the most complicated operation over finite field GF(2m) which requires a huge amount of logic resources. In this paper, a new modified serial-in parallel-out multiplication algorithm with interleaved modular reduction is suggested. The proposed method offers efficient area architecture as compared to proposed algorithms in the literature. The reduced finite field multiplier complexity is achieved by means of utilizing logic NAND gate in a particular architecture. The efficiency of the proposed architecture is evaluated based on criteria such as time (latency, critical path) and space (gate-latch number) complexity. A detailed comparative analysis indicates that, the proposed finite field multiplier based on logic NAND gate outperforms previously known results

cs.IT↗

arXiv2023

Efficient Fault Detection Architecture of Bit-Parallel Multiplier in Polynomial Basis of GF(2m) Using BCH Code

The finite field multiplier is mainly used in many of today's state of the art digital systems and its hardware implementation for bit parallel operation may require millions of logic gates. Natural causes or soft errors in digital design could cause some of these gates to malfunction in the field, which could cause the multiplier to produce incorrect outputs. To ensure that they are not susceptible to error, it is crucial to use a finite field multiplier implementation that is effective and has a high fault detection capability. In this paper, we propose a novel fault detection scheme for a recent bit-parallel polynomial basis multiplier over GF(2m), where the proposed method aims at obtaining high fault detection performance for finite field multipliers and meanwhile maintain low-complexity implementation which is favored in resource constrained applications such as smart cards. The proposed method is based on BCH error correction codes, with an area-delay efficient architecture. The experimental results show that for 45-bit multiplier with 5-bit errors the proposed error detection and correction architecture results in 37% and %49 reduction in critical path delay with compared to the existing method in [18]. Moreover, the area overhead for 45-bit multiplier with 5 errors is within 80% which is significantly lower than the best existing BCH based fault detection method in finite field multiplier [18].

cs.IT↗